src/mainboard/tyan/s2735/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #include <stdint.h>
   5 #include <string.h>
   6 #include <device/pci_def.h>
   7 #include <arch/io.h>
   8 #include <device/pnp_def.h>
   9 #include <arch/romcc_io.h>
  10 #include <cpu/x86/lapic.h>
  11 #include "option_table.h"
  12 #include "pc80/mc146818rtc_early.c"
  13 #include "pc80/serial.c"
  14 #include "arch/i386/lib/console.c"
  15 #include "lib/ramtest.c"
  16
  17 #if 0
  18 static void post_code(uint8_t value) {
  19 #if 1
  20         int i;
  21         for(i=0;i<0x80000;i++) {
  22                 outb(value, 0x80);
  23         }
  24 #endif
  25 }
  26 #endif
  27
  28 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  29 #include "northbridge/intel/e7501/raminit.h"
  30
  31 #include "cpu/x86/lapic/boot_cpu.c"
  32 #include "northbridge/intel/e7501/debug.c"
  33 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  34
  35 #include "cpu/x86/mtrr/earlymtrr.c"
  36 #include "cpu/x86/bist.h"
  37
  38 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  39
  40 // FIXME: There's another hard_reset() in reset.c. Why?
  41 static void hard_reset(void)
  42 {
  43         /* full reset */
  44         outb(0x0a, 0x0cf9);
  45         outb(0x0e, 0x0cf9);
  46 }
  47
  48 static void soft_reset(void)
  49 {
  50 #if 1
  51         /* link reset */
  52         outb(0x02, 0x0cf9);
  53         outb(0x06, 0x0cf9);
  54 #endif
  55 }
  56
  57 static void memreset_setup(void)
  58 {
  59 }
  60
  61 static void memreset(int controllers, const struct mem_controller *ctrl)
  62 {
  63 }
  64
  65 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  66 {
  67         /* nothing to do */
  68 }
  69
  70 static inline int spd_read_byte(unsigned device, unsigned address)
  71 {
  72         return smbus_read_byte(device, address);
  73 }
  74
  75
  76 #include "northbridge/intel/e7501/raminit.c"
  77 #include "northbridge/intel/e7501/reset_test.c"
  78 #include "lib/generic_sdram.c"
  79
  80
  81 #include "cpu/x86/car/copy_and_run.c"
  82
  83 void amd64_main(unsigned long bist)
  84 {
  85         static const struct mem_controller memctrl[] = {
  86                 {
  87                         .d0 = PCI_DEV(0, 0, 0),
  88                         .d0f1 = PCI_DEV(0, 0, 1),
  89                         .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
  90                         .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
  91                 },
  92         };
  93
  94         unsigned cpu_reset = 0;
  95
  96        if (bist == 0)
  97         {
  98 //              early_mtrr_init();
  99                 enable_lapic();
 100
 101         }
 102
 103 //      post_code(0x32);
 104
 105         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 106         uart_init();
 107         console_init();
 108
 109         /* Halt if there was a built in self test failure */
 110         report_bist_failure(bist);
 111
 112 //        setup_s2735_resource_map();
 113
 114         if(bios_reset_detected()) {
 115                 cpu_reset = 1;
 116                 goto cpu_reset_x;
 117         }
 118
 119         enable_smbus();
 120 #if 0
 121         dump_spd_registers(&memctrl[0]);
 122 #endif
 123 #if 0
 124         dump_smbus_registers();
 125 #endif
 126
 127         memreset_setup();
 128         sdram_initialize(1, memctrl);
 129
 130 #if 0
 131         dump_pci_devices();
 132 #endif
 133
 134 #if 1
 135         dump_pci_device(PCI_DEV(0, 0, 0));
 136 #endif
 137
 138
 139 #if 1
 140         {
 141                 /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
 142                 unsigned v_esp;
 143                 __asm__ volatile (
 144                         "movl   %%esp, %0\n\t"
 145                         : "=a" (v_esp)
 146                 );
 147 #if CONFIG_USE_INIT
 148                 printk_debug("v_esp=%08x\r\n", v_esp);
 149 #else
 150                 print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
 151 #endif
 152         }
 153
 154 #endif
 155 #if 1
 156
 157 cpu_reset_x:
 158
 159 #if CONFIG_USE_INIT
 160         printk_debug("cpu_reset = %08x\r\n",cpu_reset);
 161 #else
 162         print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
 163 #endif
 164
 165         if(cpu_reset == 0) {
 166                 print_debug("Clearing initial memory region: ");
 167         }
 168         print_debug("No cache as ram now - ");
 169
 170         /* store cpu_reset to ebx */
 171         __asm__ volatile (
 172                 "movl %0, %%ebx\n\t"
 173                 ::"a" (cpu_reset)
 174         );
 175
 176         if(cpu_reset==0) {
 177 #define CLEAR_FIRST_1M_RAM 1
 178 #include "cpu/x86/car/cache_as_ram_post.c"
 179         }
 180         else {
 181 #undef CLEAR_FIRST_1M_RAM
 182 #include "cpu/x86/car/cache_as_ram_post.c"
 183         }
 184
 185         __asm__ volatile (
 186                 /* set new esp */ /* before CONFIG_RAMBASE */
 187                 "subl   %0, %%ebp\n\t"
 188                 "subl   %0, %%esp\n\t"
 189                 ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE )
 190         );
 191
 192         {
 193                 unsigned new_cpu_reset;
 194
 195                 /* get back cpu_reset from ebx */
 196                 __asm__ volatile (
 197                         "movl %%ebx, %0\n\t"
 198                         :"=a" (new_cpu_reset)
 199                 );
 200
 201                 /* We can not go back any more, we lost old stack data in cache as ram*/
 202                 if(new_cpu_reset==0) {
 203                         print_debug("Use Ram as Stack now - done\r\n");
 204                 } else
 205                 {
 206                         print_debug("Use Ram as Stack now - \r\n");
 207                 }
 208 #if CONFIG_USE_INIT
 209                 printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
 210 #else
 211                 print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
 212 #endif
 213
 214 #ifdef DEACTIVATE_CAR
 215                 print_debug("Deactivating CAR");
 216 #include DEACTIVATE_CAR_FILE
 217                 print_debug(" - Done.\r\n");
 218 #endif
 219                 /*copy and execute coreboot_ram */
 220                 copy_and_run(new_cpu_reset);
 221                 /* We will not return */
 222         }
 223 #endif
 224
 225
 226         print_debug("should not be here -\r\n");
 227
 228 }