1 uses CONFIG_HAVE_MP_TABLE
3 uses CONFIG_HAVE_PIRQ_TABLE
4 uses CONFIG_USE_FALLBACK_IMAGE
5 uses CONFIG_HAVE_FALLBACK_BOOT
6 uses CONFIG_HAVE_HARD_RESET
7 uses CONFIG_IRQ_SLOT_COUNT
8 uses CONFIG_HAVE_OPTION_TABLE
11 uses CONFIG_MAX_PHYSICAL_CPUS
12 uses CONFIG_LOGICAL_CPUS
13 uses CONFIG_SERIAL_CPU_INIT
16 uses CONFIG_FALLBACK_SIZE
18 uses CONFIG_ROM_SECTION_SIZE
19 uses CONFIG_ROM_IMAGE_SIZE
20 uses CONFIG_ROM_SECTION_SIZE
21 uses CONFIG_ROM_SECTION_OFFSET
22 uses CONFIG_ROM_PAYLOAD
23 uses CONFIG_ROM_PAYLOAD_START
24 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
25 uses CONFIG_PRECOMPRESSED_PAYLOAD
26 uses CONFIG_PAYLOAD_SIZE
28 uses CONFIG_XIP_ROM_SIZE
29 uses CONFIG_XIP_ROM_BASE
30 uses CONFIG_STACK_SIZE
32 uses CONFIG_USE_OPTION_TABLE
33 uses CONFIG_LB_CKS_RANGE_START
34 uses CONFIG_LB_CKS_RANGE_END
35 uses CONFIG_LB_CKS_LOC
36 uses CONFIG_MAINBOARD_PART_NUMBER
37 uses CONFIG_MAINBOARD_VENDOR
39 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
40 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
41 uses COREBOOT_EXTRA_VERSION
44 uses CONFIG_CROSS_COMPILE
48 uses CONFIG_TTYS0_BAUD
49 uses CONFIG_TTYS0_BASE
51 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
52 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
53 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
54 uses CONFIG_CONSOLE_SERIAL8250
55 uses CONFIG_UDELAY_TSC
56 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
57 uses CONFIG_CONSOLE_BTEXT
58 uses CONFIG_HAVE_INIT_TIMER
60 uses CONFIG_CONSOLE_VGA
61 uses CONFIG_PCI_ROM_RUN
63 uses CONFIG_USE_DCACHE_RAM
64 uses CONFIG_DCACHE_RAM_BASE
65 uses CONFIG_DCACHE_RAM_SIZE
66 uses CONFIG_USE_PRINTK_IN_CAR
68 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
70 default CONFIG_ROM_SIZE=524288
73 #default CONFIG_ROM_SIZE=1048576
77 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
79 default CONFIG_FALLBACK_SIZE=131072
86 ## Build code for the fallback boot
88 default CONFIG_HAVE_FALLBACK_BOOT=1
91 ## Build code to reset the motherboard from coreboot
93 default CONFIG_HAVE_HARD_RESET=1
95 ## Delay timer options
97 default CONFIG_UDELAY_TSC=1
98 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
101 ## Build code to export a programmable irq routing table
103 default CONFIG_HAVE_PIRQ_TABLE=1
104 default CONFIG_IRQ_SLOT_COUNT=15
107 ## Build code to export an x86 MP table
108 ## Useful for specifying IRQ routing values
110 default CONFIG_HAVE_MP_TABLE=1
113 ## Build code to export a CMOS option table
115 default CONFIG_HAVE_OPTION_TABLE=1
118 ## Move the default coreboot cmos range off of AMD RTC registers
120 default CONFIG_LB_CKS_RANGE_START=49
121 default CONFIG_LB_CKS_RANGE_END=122
122 default CONFIG_LB_CKS_LOC=123
125 ## Build code for SMP support
126 ## Only worry about 2 micro processors
129 default CONFIG_MAX_CPUS=4
130 default CONFIG_MAX_PHYSICAL_CPUS=2
131 default CONFIG_LOGICAL_CPUS=1
133 default CONFIG_SERIAL_CPU_INIT=0
136 #default CONFIG_CONSOLE_BTEXT=1
139 #default CONFIG_CONSOLE_VGA=1
140 #default CONFIG_PCI_ROM_RUN=1
143 ## enable CACHE_AS_RAM specifics
145 default CONFIG_USE_DCACHE_RAM=1
146 #default CONFIG_DCACHE_RAM_BASE=0xF2000000
147 default CONFIG_DCACHE_RAM_BASE=0xcf000
148 default CONFIG_DCACHE_RAM_SIZE=0x1000
149 default CONFIG_USE_PRINTK_IN_CAR=1
153 ## Build code to setup a generic IOAPIC
155 default CONFIG_IOAPIC=1
158 ## Clean up the motherboard id strings
160 default CONFIG_MAINBOARD_PART_NUMBER="s2735"
161 default CONFIG_MAINBOARD_VENDOR="Tyan"
162 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
163 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2735
166 ### coreboot layout values
169 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
170 default CONFIG_ROM_IMAGE_SIZE = 65536
173 ## Use a small 8K stack
175 default CONFIG_STACK_SIZE=0x2000
178 ## Use a small 16K heap
180 default CONFIG_HEAP_SIZE=0x4000
183 ## Only use the option table in a normal image
185 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
188 ## Coreboot C code runs at this location in RAM
190 default CONFIG_RAMBASE=0x00004000
193 ## Load the payload from the ROM
195 default CONFIG_ROM_PAYLOAD = 1
198 ### Defaults of options that you may want to override in the target config file
202 ## The default compiler
204 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
208 ## Disable the gdb stub by default
210 default CONFIG_GDB_STUB=0
213 ## The Serial Console
216 # To Enable the Serial Console
217 default CONFIG_CONSOLE_SERIAL8250=1
219 ## Select the serial console baud rate
220 default CONFIG_TTYS0_BAUD=115200
221 #default CONFIG_TTYS0_BAUD=57600
222 #default CONFIG_TTYS0_BAUD=38400
223 #default CONFIG_TTYS0_BAUD=19200
224 #default CONFIG_TTYS0_BAUD=9600
225 #default CONFIG_TTYS0_BAUD=4800
226 #default CONFIG_TTYS0_BAUD=2400
227 #default CONFIG_TTYS0_BAUD=1200
229 # Select the serial console base port
230 default CONFIG_TTYS0_BASE=0x3f8
232 # Select the serial protocol
233 # This defaults to 8 data bits, 1 stop bit, and no parity
234 default CONFIG_TTYS0_LCS=0x3
237 ### Select the coreboot loglevel
239 ## EMERG 1 system is unusable
240 ## ALERT 2 action must be taken immediately
241 ## CRIT 3 critical conditions
242 ## ERR 4 error conditions
243 ## WARNING 5 warning conditions
244 ## NOTICE 6 normal but significant condition
245 ## INFO 7 informational
246 ## CONFIG_DEBUG 8 debug-level messages
247 ## SPEW 9 Way too many details
249 ## Request this level of debugging output
250 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
251 ## At a maximum only compile in this level of debugging
252 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
255 ## Select power on after power fail setting
256 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
263 default CONFIG_CBFS=0