1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/nofailovercalculation.lb
4 default CONFIG_ROM_PAYLOAD = 1
9 ## Build the objects we have code for in this directory.
13 if CONFIG_GENERATE_MP_TABLE object mptable.o end
14 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
15 if CONFIG_HAVE_HARD_RESET object reset.o end
19 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
20 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
26 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
27 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
28 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
29 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
35 ## Build our 16 bit and 32 bit coreboot entry code
37 mainboardinit cpu/x86/16bit/entry16.inc
38 mainboardinit cpu/x86/32bit/entry32.inc
39 ldscript /cpu/x86/16bit/entry16.lds
41 ldscript /cpu/x86/32bit/entry32.lds
45 ldscript /cpu/x86/car/cache_as_ram.lds
50 ## Build our reset vector (This is where coreboot is entered)
52 if CONFIG_USE_FALLBACK_IMAGE
53 mainboardinit cpu/x86/16bit/reset16.inc
54 ldscript /cpu/x86/16bit/reset16.lds
56 mainboardinit cpu/x86/32bit/reset32.inc
57 ldscript /cpu/x86/32bit/reset32.lds
61 ## Include an id string (For safe flashing)
63 mainboardinit arch/i386/lib/id.inc
64 ldscript /arch/i386/lib/id.lds
69 mainboardinit cpu/x86/car/cache_as_ram.inc
72 ### This is the early phase of coreboot startup
73 ### Things are delicate and we test to see if we should
74 ### failover to another image.
76 if CONFIG_USE_FALLBACK_IMAGE
77 ldscript /arch/i386/lib/failover.lds
86 mainboardinit ./auto.inc
90 ## Include the secondary Configuration files
94 # sample config for tyan/s2735
95 chip northbridge/intel/e7501
96 device pci_domain 0 on
100 chip southbridge/intel/i82870
101 device pci 1c.0 on end
103 device pci 1.0 on end # intel lan
104 device pci 1.1 on end
106 device pci 1e.0 on end
107 device pci 1f.0 on end
110 device pci 6.0 on end
111 chip southbridge/intel/i82801er
112 device pci 1d.0 on end
113 device pci 1d.1 on end
114 device pci 1d.2 on end
115 device pci 1d.3 on end
116 device pci 1d.7 on end
118 device pci 1.0 on end # intel lan 10/100
119 device pci 2.0 on end # ati
122 chip superio/winbond/w83627hf
123 device pnp 2e.0 on # Floppy
128 device pnp 2e.1 off # Parallel Port
132 device pnp 2e.2 on # Com1
136 device pnp 2e.3 on # Com2
140 device pnp 2e.5 on # Keyboard
146 device pnp 2e.6 off # CIR
149 device pnp 2e.7 off # GAME_MIDI_GIPO1
154 device pnp 2e.8 off end # GPIO2
155 device pnp 2e.9 off end # GPIO3
156 device pnp 2e.a off end # ACPI
157 device pnp 2e.b on # HW Monitor
163 device pci 1f.1 off end
164 device pci 1f.2 on end
165 device pci 1f.3 on end
166 device pci 1f.5 off end
167 device pci 1f.6 off end
170 device apic_cluster 0 on
171 chip cpu/intel/socket_mPGA604
174 chip cpu/intel/socket_mPGA604