2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
22 default CONFIG_XIP_ROM_SIZE = 64 * 1024
23 include /config/nofailovercalculation.lb
27 if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
29 if CONFIG_HAVE_ACPI_TABLES
35 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
36 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
38 makerule ./failover.inc
39 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
40 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
43 # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
44 depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
45 action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
48 # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
49 depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
50 action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
52 mainboardinit cpu/x86/16bit/entry16.inc
53 mainboardinit cpu/x86/32bit/entry32.inc
54 ldscript /cpu/x86/16bit/entry16.lds
55 ldscript /cpu/x86/32bit/entry32.lds
56 if CONFIG_USE_FALLBACK_IMAGE
57 mainboardinit cpu/x86/16bit/reset16.inc
58 ldscript /cpu/x86/16bit/reset16.lds
60 mainboardinit cpu/x86/32bit/reset32.inc
61 ldscript /cpu/x86/32bit/reset32.lds
63 mainboardinit arch/i386/lib/cpu_reset.inc
64 mainboardinit arch/i386/lib/id.inc
65 ldscript /arch/i386/lib/id.lds
66 if CONFIG_USE_FALLBACK_IMAGE
67 ldscript /arch/i386/lib/failover.lds
68 mainboardinit ./failover.inc
70 mainboardinit cpu/x86/fpu/enable_fpu.inc
71 mainboardinit cpu/x86/mmx/enable_mmx.inc
72 mainboardinit ./auto.inc
73 mainboardinit cpu/x86/mmx/disable_mmx.inc
77 chip northbridge/intel/i82830 # Northbridge
78 device pci_domain 0 on # PCI domain
79 device pci 0.0 on end # Host bridge
80 chip drivers/pci/onboard # Onboard VGA
81 device pci 2.0 on end # VGA (Intel 82830 CGC)
82 register "rom_address" = "0xfff00000"
84 chip southbridge/intel/i82801xx # Southbridge
85 register "pirqa_routing" = "0x05"
86 register "pirqb_routing" = "0x06"
87 register "pirqc_routing" = "0x07"
88 register "pirqd_routing" = "0x09"
89 register "pirqe_routing" = "0x0a"
90 register "pirqf_routing" = "0x80"
91 register "pirqg_routing" = "0x80"
92 register "pirqh_routing" = "0x0b"
94 register "ide0_enable" = "1"
95 register "ide1_enable" = "1"
97 device pci 1d.0 on end # USB UHCI Controller #1
98 device pci 1d.1 on end # USB UHCI Controller #2
99 device pci 1d.2 on end # USB UHCI Controller #3
100 device pci 1d.7 on end # USB2 EHCI Controller
101 device pci 1e.0 on # PCI bridge
102 device pci 08.0 on end # Intel 82801DB PRO/100 VE Ethernet
104 device pci 1f.0 on # ISA/LPC bridge
105 chip superio/smsc/smscsuperio # Super I/O
106 device pnp 2e.0 off # Floppy
111 device pnp 2e.3 on # Parallel port
116 device pnp 2e.4 on # Com1
120 device pnp 2e.5 on # Com2 / IR
124 device pnp 2e.7 on # PS/2 keyboard/mouse
127 irq 0x70 = 1 # Keyboard interrupt
128 irq 0x72 = 12 # Mouse interrupt
130 device pnp 2e.9 off end # Game port
131 device pnp 2e.a on # PME
134 device pnp 2e.b off end # MPU-401
137 device pci 1f.1 on end # IDE
138 device pci 1f.3 on end # SMBus
139 device pci 1f.5 on end # AC'97 audio
140 device pci 1f.6 off end # AC'97 modem
143 device apic_cluster 0 on # APIC cluster
144 chip cpu/intel/socket_PGA370 # Low Voltage PIII Micro-FCBGA Socket 479
145 device apic 0 on end # APIC