2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
5 default ROM_SIZE = 128 * 1024
6 default FALLBACK_SIZE = 0x10000
8 default ROM_SECTION_SIZE = FALLBACK_SIZE
9 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
11 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
12 default ROM_SECTION_OFFSET = 0
16 ## Compute the start location and size size of
17 ## The linuxBIOS bootloader.
19 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
20 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
23 ## Compute where this copy of linuxBIOS will start in the boot rom
25 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
28 ## Compute a range of ROM that can cached to speed up linuxBIOS,
31 ## XIP_ROM_SIZE must be a power of 2.
32 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
34 default XIP_ROM_SIZE=32*1024
35 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
38 ## Set all of the defaults for an x86 architecture
44 ## Build the objects we have code for in this directory.
48 if HAVE_PIRQ_TABLE object irq_tables.o end
55 depends "$(MAINBOARD)/failover.c ./romcc"
56 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
59 makerule ./failover.inc
60 depends "$(MAINBOARD)/failover.c ./romcc"
61 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
65 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
66 action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
69 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
70 action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
74 ## Build our 16 bit and 32 bit linuxBIOS entry code
76 mainboardinit cpu/x86/16bit/entry16.inc
77 mainboardinit cpu/x86/32bit/entry32.inc
78 ldscript /cpu/x86/16bit/entry16.lds
79 ldscript /cpu/x86/32bit/entry32.lds
82 ## Build our reset vector (This is where linuxBIOS is entered)
85 mainboardinit cpu/x86/16bit/reset16.inc
86 ldscript /cpu/x86/16bit/reset16.lds
88 mainboardinit cpu/x86/32bit/reset32.inc
89 ldscript /cpu/x86/32bit/reset32.lds
92 ### Should this be in the northbridge code?
93 mainboardinit arch/i386/lib/cpu_reset.inc
96 ## Include an id string (For safe flashing)
98 mainboardinit arch/i386/lib/id.inc
99 ldscript /arch/i386/lib/id.lds
102 ### This is the early phase of linuxBIOS startup
103 ### Things are delicate and we test to see if we should
104 ### failover to another image.
106 if USE_FALLBACK_IMAGE
107 ldscript /arch/i386/lib/failover.lds
108 mainboardinit ./failover.inc
113 #if CONFIG_CONSOLE_VGA
114 # default CONFIG_PCI_ROM_RUN=1
117 ### O.k. We aren't just an intermediary anymore!
123 mainboardinit cpu/x86/fpu/enable_fpu.inc
124 mainboardinit ./auto.inc
127 ## Include the secondary Configuration files
134 device pci_domain 0 on
135 device pci 0.0 on end
137 # chip drivers/pci/onboard
138 # device pci 12.0 on end # enet
140 # chip drivers/pci/onboard
141 # device pci 14.0 on end # 69000
142 # register "rom_address" = "0x2000000"
144 # register "com1" = "{1}"
145 # register "com1" = "{1, 0, 0x3f8, 4}"