src/mainboard/technexion/tim8690/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2008 Advanced Micro Devices, Inc.
   5 ##
   6 ## This program is free software; you can redistribute it and/or modify
   7 ## it under the terms of the GNU General Public License as published by
   8 ## the Free Software Foundation; version 2 of the License.
   9 ##
  10 ## This program is distributed in the hope that it will be useful,
  11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ## GNU General Public License for more details.
  14 ##
  15 ## You should have received a copy of the GNU General Public License
  16 ## along with this program; if not, write to the Free Software
  17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18 ##
  19 ##
  20 ##
  21
  22 include /config/nofailovercalculation.lb
  23
  24 arch i386 end
  25
  26 ##
  27 ## Build the objects we have code for in this directory.
  28 ##
  29
  30 driver mainboard.o
  31
  32 #dir /drivers/si/3114
  33
  34 if HAVE_MP_TABLE object mptable.o end
  35 if HAVE_PIRQ_TABLE
  36         object get_bus_conf.o
  37         object irq_tables.o
  38 end
  39
  40 if HAVE_ACPI_TABLES
  41         object acpi_tables.o
  42         object fadt.o
  43         makerule dsdt.c
  44                 depends "$(MAINBOARD)/acpi/*.asl"
  45                 action  "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl"
  46                 action  "mv dsdt.hex dsdt.c"
  47         end
  48         object ./dsdt.o
  49 end
  50
  51 #object reset.o
  52
  53         if CONFIG_USE_INIT
  54
  55                 makerule ./cache_as_ram_auto.o
  56                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  57                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  58                 end
  59
  60         else
  61
  62                 makerule ./cache_as_ram_auto.inc
  63                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  64                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  65                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  66                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  67                 end
  68
  69         end
  70
  71 ##
  72 ## Build our 16 bit and 32 bit coreboot entry code
  73 ##
  74 mainboardinit cpu/x86/16bit/entry16.inc
  75 mainboardinit cpu/x86/32bit/entry32.inc
  76 ldscript /cpu/x86/16bit/entry16.lds
  77         if CONFIG_USE_INIT
  78                 ldscript /cpu/x86/32bit/entry32.lds
  79         end
  80
  81         if CONFIG_USE_INIT
  82                 ldscript      /cpu/amd/car/cache_as_ram.lds
  83         end
  84
  85 ##
  86 ## Build our reset vector (This is where coreboot is entered)
  87 ##
  88 if USE_FALLBACK_IMAGE
  89         mainboardinit cpu/x86/16bit/reset16.inc
  90         ldscript /cpu/x86/16bit/reset16.lds
  91 else
  92         mainboardinit cpu/x86/32bit/reset32.inc
  93         ldscript /cpu/x86/32bit/reset32.lds
  94 end
  95
  96 ##
  97 ## Include an id string (For safe flashing)
  98 ##
  99 mainboardinit arch/i386/lib/id.inc
 100 ldscript /arch/i386/lib/id.lds
 101
 102         ##
 103         ## Setup Cache-As-Ram
 104         ##
 105         mainboardinit cpu/amd/car/cache_as_ram.inc
 106
 107 ###
 108 ### This is the early phase of coreboot startup
 109 ### Things are delicate and we test to see if we should
 110 ### failover to another image.
 111 ###
 112 if USE_FALLBACK_IMAGE
 113                 ldscript /arch/i386/lib/failover.lds
 114 end
 115
 116 ###
 117 ### O.k. We aren't just an intermediary anymore!
 118 ###
 119
 120 ##
 121 ## Setup RAM
 122 ##
 123         if CONFIG_USE_INIT
 124                 initobject cache_as_ram_auto.o
 125         else
 126                 mainboardinit ./cache_as_ram_auto.inc
 127         end
 128
 129 ##
 130 ## Include the secondary Configuration files
 131 ##
 132 config chip.h
 133
 134 #The variables belong to mainboard are defined here.
 135
 136 #Define gpp_configuration,      A=0, B=1, C=2, D=3, E=4(default)
 137 #Define vga_rom_address = 0xfff80000
 138 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
 139 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
 140 #                                          1: the system allows a PCIE link to be established on Dev2 or Dev3.
 141 #Define gfx_dual_slot, 0: single slot, 1: dual slot
 142 #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
 143 #Define gfx_tmds, 0: didn't support TMDS, 1: support
 144 #Define gfx_compliance, 0: didn't support compliance, 1: support
 145 #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
 146 #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
 147 chip northbridge/amd/amdk8/root_complex
 148         device apic_cluster 0 on
 149                 chip cpu/amd/socket_S1G1
 150                 device apic 0 on end
 151                 end
 152         end
 153         device pci_domain 0 on
 154                 chip northbridge/amd/amdk8
 155                         device pci 18.0 on #  southbridge
 156                                 chip southbridge/amd/rs690
 157                                         device pci 0.0 on end # HT      0x7910
 158                                         device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
 159                                                 chip drivers/pci/onboard
 160                                                         device pci 5.0 on end   # Internal Graphics 0x791F
 161                                                         register "rom_address" = "0xfff80000"
 162                                                 end
 163                                         end
 164                                         device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
 165                                         device pci 3.0 off end # PCIE P2P bridge        0x791b
 166                                         device pci 4.0 on end # PCIE P2P bridge 0x7914
 167                                         device pci 5.0 on end # PCIE P2P bridge 0x7915
 168                                         device pci 6.0 on end # PCIE P2P bridge 0x7916
 169                                         device pci 7.0 on end # PCIE P2P bridge 0x7917
 170                                         device pci 8.0 off end # NB/SB Link P2P bridge
 171                                         register "vga_rom_address" = "0xfff80000"
 172                                         register "gpp_configuration" = "4"
 173                                         register "port_enable" = "0xfc"
 174                                         register "gfx_dev2_dev3" = "1"
 175                                         register "gfx_dual_slot" = "0"
 176                                         register "gfx_lane_reversal" = "0"
 177                                         register "gfx_tmds" = "0"
 178                                         register "gfx_compliance" = "0"
 179                                         register "gfx_reconfiguration" = "1"
 180                                         register "gfx_link_width" = "0"
 181                                 end
 182                                 chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
 183                                         device pci 12.0 on end # SATA  0x4380
 184                                         device pci 13.0 on end # USB   0x4387
 185                                         device pci 13.1 on end # USB   0x4388
 186                                         device pci 13.2 on end # USB   0x4389
 187                                         device pci 13.3 on end # USB   0x438a
 188                                         device pci 13.4 on end # USB   0x438b
 189                                         device pci 13.5 on end # USB 2 0x4386
 190                                         device pci 14.0 on # SM        0x4385
 191                                                 chip drivers/generic/generic #dimm 0-0-0
 192                                                         device i2c 50 on end
 193                                                 end
 194                                                 chip drivers/generic/generic #dimm 0-0-1
 195                                                         device i2c 51 on end
 196                                                 end
 197                                                 chip drivers/generic/generic #dimm 0-1-0
 198                                                         device i2c 52 on end
 199                                                 end
 200                                                 chip drivers/generic/generic #dimm 0-1-1
 201                                                         device i2c 53 on end
 202                                                 end
 203                                         end # SM
 204                                         device pci 14.1 on end # IDE    0x438c
 205                                         device pci 14.2 on end # HDA    0x4383
 206                                         device pci 14.3 on # LPC        0x438d
 207                                                 chip superio/ite/it8712f
 208                                                         device pnp 2e.0 off #  Floppy
 209                                                                 io 0x60 = 0x3f0
 210                                                                 irq 0x70 = 6
 211                                                                 drq 0x74 = 2
 212                                                         end
 213                                                         device pnp 2e.1 on #  Com1
 214                                                                 io 0x60 = 0x3f8
 215                                                                 irq 0x70 = 4
 216                                                         end
 217                                                         device pnp 2e.2 off #  Com2
 218                                                                 io 0x60 = 0x2f8
 219                                                                 irq 0x70 = 3
 220                                                         end
 221                                                         device pnp 2e.3 off #  Parallel Port
 222                                                                 io 0x60 = 0x378
 223                                                                 irq 0x70 = 7
 224                                                         end
 225                                                         device pnp 2e.4 off end #  EC
 226                                                         device pnp 2e.5 on #  Keyboard
 227                                                                 io 0x60 = 0x60
 228                                                                 io 0x62 = 0x64
 229                                                                 irq 0x70 = 1
 230                                                         end
 231                                                         device pnp 2e.6 on #  Mouse
 232                                                                 irq 0x70 = 12
 233                                                         end
 234                                                         device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
 235                                                         end
 236                                                         device pnp 2e.8 off #  MIDI
 237                                                                 io 0x60 = 0x300
 238                                                                 irq 0x70 = 9
 239                                                         end
 240                                                         device pnp 2e.9 off #  GAME
 241                                                                 io 0x60 = 0x220
 242                                                         end
 243                                                         device pnp 2e.a off end #  CIR
 244                                                 end     #superio/ite/it8712f
 245                                         end             #LPC
 246                                         device pci 14.4 on end # PCI 0x4384
 247                                         device pci 14.5 on end # ACI 0x4382
 248                                         device pci 14.6 on end # MCI 0x438e
 249                                         register "ide0_enable" = "1"
 250                                         register "sata0_enable" = "1"
 251                                         register "hda_viddid" = "0x10ec0882"
 252                                 end     #southbridge/amd/sb600
 253                         end #  device pci 18.0
 254
 255                         device pci 18.0 on end
 256                         device pci 18.0 on end
 257                         device pci 18.1 on end
 258                         device pci 18.2 on end
 259                         device pci 18.3 on end
 260                 end             #northbridge/amd/amdk8
 261         end #pci_domain
 262 end             #northbridge/amd/amdk8/root_complex
 263