2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
24 #include <boot/tables.h>
25 #include <cpu/x86/msr.h>
26 #include <cpu/amd/mtrr.h>
27 #include <device/pci_def.h>
28 #include <southbridge/amd/sb600/sb600.h>
29 #include <superio/ite/it8712f/it8712f.h>
31 #include "tn_post_code.h"
34 #define ADT7461_ADDRESS 0x4C
35 #define ARA_ADDRESS 0x0C /* Alert Response Address */
36 #define SMBUS_IO_BASE 0x1000
39 /* Video BIOS Function Extensions Specification
41 //Callback Sub-Function 00h - Get LCD Panel ID
42 #define LCD_PANEL_ID_NO 0x00 /* No LCD */
43 #define LCD_PANEL_ID_01 0x01 /* 1024x768, 24 bits, 1 channel */
44 #define LCD_PANEL_ID_02 0x02 /* 1280x1024, 24 bits, 2 channels */
45 #define LCD_PANEL_ID_03 0x03 /* 1440x900, 24 bits, 2 channels */
46 #define LCD_PANEL_ID_04 0x04 /* 1680x1050, 24 bits, 2 channels */
47 #define LCD_PANEL_ID_05 0x05 /* 1920x1200, 24 bits, 2 channels */
48 #define LCD_PANEL_ID_06 0x06 /* 1920x1080, 24 bits, 2 channels */
49 //Callback Sub-Function 05h – Select Boot-up TV Standard
50 #define TV_MODE_00 0x00 /* NTSC */
51 #define TV_MODE_01 0x01 /* PAL */
52 #define TV_MODE_02 0x02 /* PALM */
53 #define TV_MODE_03 0x03 /* PAL60 */
54 #define TV_MODE_04 0x04 /* NTSCJ */
55 #define TV_MODE_05 0x05 /* PALCN */
56 #define TV_MODE_06 0x06 /* PALN */
57 #define TV_MODE_09 0x09 /* SCART-RGB */
58 #define TV_MODE_NO 0xff /* No TV Support */
60 /* The base address is 0x2e or 0x4e, depending on config bytes. */
62 #define SIO_INDEX SIO_BASE
63 #define SIO_DATA SIO_BASE+1
65 /* Global configuration registers. */
66 #define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
67 #define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
68 #define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
69 #define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
70 #define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
71 #define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */
72 #define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
74 #define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */
75 #define IT8712F_SIMPLE_IO_BASE 0x200 /* Simple I/O base address */
77 int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
78 int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
79 #define ADT7461_read_byte(address) \
80 do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
81 #define ARA_read_byte(address) \
82 do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
83 #define ADT7461_write_byte(address, val) \
84 do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
86 uint64_t uma_memory_base, uma_memory_size;
88 /* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
89 LDN the register belongs to, before you can access the register. */
90 static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
92 outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
94 outb(index, SIO_BASE);
95 outb(value, SIO_DATA);
98 static void it8712f_enter_conf(void)
100 /* Enter the configuration state (MB PnP mode). */
102 /* Perform MB PnP setup to put the SIO chip at 0x2e. */
103 /* Base address 0x2e: 0x87 0x01 0x55 0x55. */
104 /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
105 outb(0x87, IT8712F_CONFIGURATION_PORT);
106 outb(0x01, IT8712F_CONFIGURATION_PORT);
107 outb(0x55, IT8712F_CONFIGURATION_PORT);
108 outb(0x55, IT8712F_CONFIGURATION_PORT);
111 static void it8712f_exit_conf(void)
113 /* Exit the configuration state (MB PnP mode). */
114 it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
117 /* set thermal config
119 static void set_thermal_config(void)
126 ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
127 ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
128 ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
129 ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
131 ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
132 ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
134 byte = ADT7461_read_byte(0x02); /* read status register to clear it */
135 ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
136 printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
138 /* sb600 settings for thermal config */
139 /* set SB600 GPIO 64 to GPIO with pull-up */
140 byte = pm2_ioread(0x42);
142 pm2_iowrite(0x42, byte);
144 /* set GPIO 64 to input */
145 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
146 word = pci_read_config16(sm_dev, 0x56);
148 pci_write_config16(sm_dev, 0x56, word);
150 /* set GPIO 64 internal pull-up */
151 byte = pm2_ioread(0xf0);
153 pm2_iowrite(0xf0, byte);
155 /* set Talert to be active low */
156 byte = pm_ioread(0x67);
158 pm_iowrite(0x67, byte);
160 /* set Talert to generate ACPI event */
161 byte = pm_ioread(0x3c);
163 pm_iowrite(0x3c, byte);
166 /* byte = pm_ioread(0x68);
168 * pm_iowrite(0x68, byte);
170 * byte = pm_ioread(0x55);
172 * pm_iowrite(0x55, byte);
174 * byte = pm_ioread(0x67);
175 * byte &= ~( 1 << 6);
176 * pm_iowrite(0x67, byte);
180 /* Mainboard specific GPIO setup. */
181 static void mb_gpio_init(u16 *iobase)
183 /* Init Super I/O GPIOs. */
184 it8712f_enter_conf();
185 outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX);
186 outb(IT8712F_GPIO, SIO_DATA);
187 outb(0x62, SIO_INDEX);
188 outb((*iobase >> 8), SIO_DATA);
189 outb(0x63, SIO_INDEX);
190 outb((*iobase & 0xff), SIO_DATA);
194 /* The LCD's panel id seletion. */
195 static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
199 vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_01;
202 vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_02;
205 vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_03;
208 vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_04;
211 vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_05;
214 vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_06;
217 vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_NO;
222 /*************************************************
223 * enable the dedicated function in tim5690 board.
224 * This function called early than rs690_enable.
225 *************************************************/
226 static void tim5690_enable(device_t dev)
228 rs690_vbios_regs vbios_regs;
229 u16 gpio_base = IT8712F_SIMPLE_IO_BASE;
232 printk(BIOS_INFO, "Mainboard tim5690 Enable. dev=0x%p\n", dev);
234 mb_gpio_init(&gpio_base);
236 /* The LCD's panel id seletion by switch. */
237 port2 = inb(gpio_base+1);
238 lcd_panel_id(&vbios_regs, ((~port2) & 0xf));
241 vbios_regs.int15_regs.fun05_tv_standard = TV_MODE_NO;
242 vgabios_init(&vbios_regs);
244 #if (CONFIG_GFXUMA == 1)
247 /* TOP_MEM: the top of DRAM below 4G */
248 msr = rdmsr(TOP_MEM);
249 printk(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
250 __func__, msr.lo, msr.hi);
252 /* TOP_MEM2: the top of DRAM above 4G */
253 msr2 = rdmsr(TOP_MEM2);
254 printk(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
255 __func__, msr2.lo, msr2.hi);
258 case 0x10000000: /* 256M system memory */
259 uma_memory_size = 0x2000000; /* 32M recommended UMA */
262 case 0x18000000: /* 384M system memory */
263 uma_memory_size = 0x4000000; /* 64M recommended UMA */
266 case 0x20000000: /* 512M system memory */
267 uma_memory_size = 0x4000000; /* 64M recommended UMA */
270 default: /* 1GB and above system memory */
271 uma_memory_size = 0x8000000; /* 128M recommended UMA */
275 uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
276 printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
277 __func__, uma_memory_size, uma_memory_base);
281 uma_memory_size = 0x8000000; /* 128M recommended UMA */
282 uma_memory_base = 0x38000000; /* 1GB system memory supposed */
285 set_thermal_config();
288 int add_mainboard_resources(struct lb_memory *mem)
290 /* UMA is removed from system memory in the northbridge code, but
291 * in some circumstances we want the memory mentioned as reserved.
293 #if (CONFIG_GFXUMA == 1)
294 printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
295 uma_memory_base, uma_memory_size);
296 lb_add_memory_range(mem, LB_MEM_RESERVED,
297 uma_memory_base, uma_memory_size);
299 technexion_post_code(LED_MESSAGE_FINISH);
303 struct chip_operations mainboard_ops = {
304 CHIP_NAME("TechNexion TIM-5690 Mainboard")
305 .enable_dev = tim5690_enable,