2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Advanced Micro Devices, Inc.
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 uses CONFIG_GENERATE_MP_TABLE
23 uses CONFIG_GENERATE_PIRQ_TABLE
24 uses CONFIG_GENERATE_ACPI_TABLES
25 uses CONFIG_HAVE_ACPI_RESUME
26 uses CONFIG_USE_FALLBACK_IMAGE
27 uses CONFIG_HAVE_FALLBACK_BOOT
28 uses CONFIG_HAVE_HARD_RESET
29 uses CONFIG_IRQ_SLOT_COUNT
30 uses CONFIG_HAVE_OPTION_TABLE
32 uses CONFIG_MAX_PHYSICAL_CPUS
33 uses CONFIG_LOGICAL_CPUS
36 uses CONFIG_FALLBACK_SIZE
38 uses CONFIG_ROM_SECTION_SIZE
39 uses CONFIG_ROM_IMAGE_SIZE
40 uses CONFIG_ROM_SECTION_SIZE
41 uses CONFIG_ROM_SECTION_OFFSET
42 uses CONFIG_ROM_PAYLOAD
43 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
45 uses CONFIG_XIP_ROM_SIZE
46 uses CONFIG_XIP_ROM_BASE
47 uses CONFIG_STACK_SIZE
49 uses CONFIG_USE_OPTION_TABLE
50 uses CONFIG_LB_CKS_RANGE_START
51 uses CONFIG_LB_CKS_RANGE_END
52 uses CONFIG_LB_CKS_LOC
53 uses CONFIG_MAINBOARD_PART_NUMBER
54 uses CONFIG_MAINBOARD_VENDOR
56 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
57 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
58 uses COREBOOT_EXTRA_VERSION
60 uses CONFIG_TTYS0_BAUD
61 uses CONFIG_TTYS0_BASE
63 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
64 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
65 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
66 uses CONFIG_CONSOLE_SERIAL8250
67 uses CONFIG_HAVE_INIT_TIMER
70 uses CONFIG_CROSS_COMPILE
74 uses CONFIG_CONSOLE_VGA
75 uses CONFIG_PCI_ROM_RUN
76 uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE
77 uses CONFIG_HW_MEM_HOLE_SIZEK
78 uses CONFIG_HT_CHAIN_UNITID_BASE
79 uses CONFIG_HT_CHAIN_END_UNITID_BASE
80 uses CONFIG_SB_HT_CHAIN_ON_BUS0
82 uses CONFIG_USE_DCACHE_RAM
83 uses CONFIG_DCACHE_RAM_BASE
84 uses CONFIG_DCACHE_RAM_SIZE
85 uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
88 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
89 uses CONFIG_USE_PRINTK_IN_CAR
93 uses CONFIG_HAVE_MAINBOARD_RESOURCES
94 uses CONFIG_VGA_ROM_RUN
101 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
103 default CONFIG_ROM_SIZE=524288
106 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
108 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
111 ## Build code for the fallback boot
113 default CONFIG_HAVE_FALLBACK_BOOT=1
116 ## Build code to reset the motherboard from coreboot
118 default CONFIG_HAVE_HARD_RESET=1
121 ## Build code to export a programmable irq routing table
123 default CONFIG_GENERATE_PIRQ_TABLE=1
124 default CONFIG_IRQ_SLOT_COUNT=11
127 ## Build code to export an x86 MP table
128 ## Useful for specifying IRQ routing values
130 default CONFIG_GENERATE_MP_TABLE=1
132 ## ACPI tables will be included
133 default CONFIG_GENERATE_ACPI_TABLES=1
136 ## Build code to export a CMOS option table
138 default CONFIG_HAVE_OPTION_TABLE=0
141 ## Move the default coreboot cmos range off of AMD RTC registers
143 default CONFIG_LB_CKS_RANGE_START=49
144 default CONFIG_LB_CKS_RANGE_END=122
145 default CONFIG_LB_CKS_LOC=123
148 ## Build code for SMP support
149 ## Only worry about 2 micro processors
152 default CONFIG_MAX_CPUS=2
154 default CONFIG_MAX_PHYSICAL_CPUS=1
155 default CONFIG_LOGICAL_CPUS=1
158 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
161 default CONFIG_CONSOLE_VGA=1
162 default CONFIG_PCI_ROM_RUN=1
163 default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1
164 default CONFIG_VGA_ROM_RUN=1
166 # BTDC: Only one HT device on Herring.
168 #default CONFIG_HT_CHAIN_UNITID_BASE=0x6
169 default CONFIG_HT_CHAIN_UNITID_BASE=0x0
173 default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
175 #make the SB HT chain on bus 0
176 default CONFIG_SB_HT_CHAIN_ON_BUS0=1
179 ## enable CACHE_AS_RAM specifics
181 default CONFIG_USE_DCACHE_RAM=1
182 default CONFIG_DCACHE_RAM_BASE=0xc8000
183 default CONFIG_DCACHE_RAM_SIZE=0x8000
184 default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
185 default CONFIG_USE_INIT=0
188 ## Build code to setup a generic IOAPIC
190 default CONFIG_IOAPIC=1
193 ## Clean up the motherboard id strings
195 default CONFIG_MAINBOARD_PART_NUMBER="tim5690"
196 default CONFIG_MAINBOARD_VENDOR="technexion"
197 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
198 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
202 ### coreboot layout values
205 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
206 default CONFIG_ROM_IMAGE_SIZE = 65536
209 ## Use a small 8K stack
211 default CONFIG_STACK_SIZE=0x2000
214 ## Use a small 16K heap
216 default CONFIG_HEAP_SIZE=0x4000
219 ## Only use the option table in a normal image
221 #default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
222 default CONFIG_USE_OPTION_TABLE = 0
225 ## coreboot C code runs at this location in RAM
227 default CONFIG_RAMBASE=0x00004000
230 ## Load the payload from the ROM
232 default CONFIG_ROM_PAYLOAD = 1
235 ### Defaults of options that you may want to override in the target config file
239 ## The default compiler
241 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
245 ## Disable the gdb stub by default
247 default CONFIG_GDB_STUB=0
250 default CONFIG_USE_PRINTK_IN_CAR=1
253 ## The Serial Console
256 # To Enable the Serial Console
257 default CONFIG_CONSOLE_SERIAL8250=1
259 ## Select the serial console baud rate
260 default CONFIG_TTYS0_BAUD=115200
261 #default CONFIG_TTYS0_BAUD=57600
262 #default CONFIG_TTYS0_BAUD=38400
263 #default CONFIG_TTYS0_BAUD=19200
264 #default CONFIG_TTYS0_BAUD=9600
265 #default CONFIG_TTYS0_BAUD=4800
266 #default CONFIG_TTYS0_BAUD=2400
267 #default CONFIG_TTYS0_BAUD=1200
269 # Select the serial console base port
270 default CONFIG_TTYS0_BASE=0x3f8
272 # Select the serial protocol
273 # This defaults to 8 data bits, 1 stop bit, and no parity
274 default CONFIG_TTYS0_LCS=0x3
277 ### Select the coreboot loglevel
279 ## EMERG 1 system is unusable
280 ## ALERT 2 action must be taken immediately
281 ## CRIT 3 critical conditions
282 ## ERR 4 error conditions
283 ## WARNING 5 warning conditions
284 ## NOTICE 6 normal but significant condition
285 ## INFO 7 informational
286 ## CONFIG_DEBUG 8 debug-level messages
287 ## SPEW 9 Way too many details
289 ## Request this level of debugging output
290 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
291 ## At a maximum only compile in this level of debugging
292 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
295 ## Select power on after power fail setting
296 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
298 default CONFIG_VIDEO_MB=1
299 default CONFIG_GFXUMA=1
300 default CONFIG_HAVE_MAINBOARD_RESOURCES=1