src/mainboard/technexion/tim5690/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2008 Advanced Micro Devices, Inc.
   5 ##
   6 ## This program is free software; you can redistribute it and/or modify
   7 ## it under the terms of the GNU General Public License as published by
   8 ## the Free Software Foundation; version 2 of the License.
   9 ##
  10 ## This program is distributed in the hope that it will be useful,
  11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ## GNU General Public License for more details.
  14 ##
  15 ## You should have received a copy of the GNU General Public License
  16 ## along with this program; if not, write to the Free Software
  17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18 ##
  19 ##
  20 ##
  21
  22 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
  23 default CONFIG_XIP_ROM_SIZE = 64 * 1024
  24 include /config/nofailovercalculation.lb
  25
  26 arch i386 end
  27
  28 ##
  29 ## Build the objects we have code for in this directory.
  30 ##
  31
  32 driver mainboard.o
  33 object vgabios.o
  34 object tn_post_code.o
  35 object speaker.o
  36
  37 #dir /drivers/si/3114
  38
  39 if CONFIG_GENERATE_MP_TABLE object mptable.o end
  40 if CONFIG_GENERATE_PIRQ_TABLE
  41         object get_bus_conf.o
  42         object irq_tables.o
  43 end
  44
  45 if CONFIG_GENERATE_ACPI_TABLES
  46         object acpi_tables.o
  47         object fadt.o
  48         makerule dsdt.c
  49                 depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
  50                 action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
  51                 action  "mv dsdt.hex dsdt.c"
  52         end
  53         object ./dsdt.o
  54 end
  55
  56         if CONFIG_USE_INIT
  57
  58                 makerule ./cache_as_ram_auto.o
  59                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  60                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  61                 end
  62
  63         else
  64
  65                 makerule ./cache_as_ram_auto.inc
  66                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  67                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  68                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  69                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  70                 end
  71
  72         end
  73
  74 ##
  75 ## Build our 16 bit and 32 bit coreboot entry code
  76 ##
  77 mainboardinit cpu/x86/16bit/entry16.inc
  78 mainboardinit cpu/x86/32bit/entry32.inc
  79 ldscript /cpu/x86/16bit/entry16.lds
  80         if CONFIG_USE_INIT
  81                 ldscript /cpu/x86/32bit/entry32.lds
  82         end
  83
  84         if CONFIG_USE_INIT
  85                 ldscript      /cpu/amd/car/cache_as_ram.lds
  86         end
  87
  88 ##
  89 ## Build our reset vector (This is where coreboot is entered)
  90 ##
  91 if CONFIG_USE_FALLBACK_IMAGE
  92         mainboardinit cpu/x86/16bit/reset16.inc
  93         ldscript /cpu/x86/16bit/reset16.lds
  94 else
  95         mainboardinit cpu/x86/32bit/reset32.inc
  96         ldscript /cpu/x86/32bit/reset32.lds
  97 end
  98
  99 ##
 100 ## Include an id string (For safe flashing)
 101 ##
 102 mainboardinit arch/i386/lib/id.inc
 103 ldscript /arch/i386/lib/id.lds
 104
 105         ##
 106         ## Setup Cache-As-Ram
 107         ##
 108         mainboardinit cpu/amd/car/cache_as_ram.inc
 109
 110 ###
 111 ### This is the early phase of coreboot startup
 112 ### Things are delicate and we test to see if we should
 113 ### failover to another image.
 114 ###
 115 if CONFIG_USE_FALLBACK_IMAGE
 116                 ldscript /arch/i386/lib/failover.lds
 117 end
 118
 119 ###
 120 ### O.k. We aren't just an intermediary anymore!
 121 ###
 122
 123 ##
 124 ## Setup RAM
 125 ##
 126         if CONFIG_USE_INIT
 127                 initobject cache_as_ram_auto.o
 128         else
 129                 mainboardinit ./cache_as_ram_auto.inc
 130         end
 131
 132 ##
 133 ## Include the secondary Configuration files
 134 ##
 135 config chip.h
 136
 137 #The variables belong to mainboard are defined here.
 138
 139 #Define gpp_configuration,      A=0, B=1, C=2, D=3, E=4(default)
 140 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
 141 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
 142 #                       1: the system allows a PCIE link to be established on Dev2 or Dev3.
 143 #Define gfx_dual_slot, 0: single slot, 1: dual slot
 144 #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
 145 #Define gfx_tmds, 0: didn't support TMDS, 1: support
 146 #Define gfx_compliance, 0: didn't support compliance, 1: support
 147 #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
 148 #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
 149 chip northbridge/amd/amdk8/root_complex
 150         device apic_cluster 0 on
 151                 chip cpu/amd/socket_S1G1
 152                 device apic 0 on end
 153                 end
 154         end
 155         device pci_domain 0 on
 156                 chip northbridge/amd/amdk8
 157                         device pci 18.0 on #  southbridge
 158                                 chip southbridge/amd/rs690
 159                                         device pci 0.0 on end # HT      0x7910
 160                                         device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
 161                                                 device pci 5.0 on end   # Internal Graphics 0x791F
 162                                         end
 163                                         device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
 164                                         device pci 3.0 off end # PCIE P2P bridge        0x791b
 165                                         device pci 4.0 on end # PCIE P2P bridge 0x7914
 166                                         device pci 5.0 on end # PCIE P2P bridge 0x7915
 167                                         device pci 6.0 on end # PCIE P2P bridge 0x7916
 168                                         device pci 7.0 on end # PCIE P2P bridge 0x7917
 169                                         device pci 8.0 off end # NB/SB Link P2P bridge
 170                                         register "gpp_configuration" = "4"
 171                                         register "port_enable" = "0xfc"
 172                                         register "gfx_dev2_dev3" = "1"
 173                                         register "gfx_dual_slot" = "0"
 174                                         register "gfx_lane_reversal" = "0"
 175                                         register "gfx_tmds" = "1"
 176                                         register "gfx_compliance" = "0"
 177                                         register "gfx_reconfiguration" = "0"
 178                                         register "gfx_link_width" = "0"
 179                                 end
 180                                 chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
 181                                         device pci 12.0 on end # SATA  0x4380
 182                                         device pci 13.0 on end # USB   0x4387
 183                                         device pci 13.1 on end # USB   0x4388
 184                                         device pci 13.2 on end # USB   0x4389
 185                                         device pci 13.3 on end # USB   0x438a
 186                                         device pci 13.4 on end # USB   0x438b
 187                                         device pci 13.5 on end # USB 2 0x4386
 188                                         device pci 14.0 on # SM        0x4385
 189                                                 chip drivers/generic/generic #dimm 0-0-0
 190                                                         device i2c 50 on end
 191                                                 end
 192                                                 chip drivers/generic/generic #dimm 0-0-1
 193                                                         device i2c 51 on end
 194                                                 end
 195                                                 chip drivers/generic/generic #dimm 0-1-0
 196                                                         device i2c 52 on end
 197                                                 end
 198                                                 chip drivers/generic/generic #dimm 0-1-1
 199                                                         device i2c 53 on end
 200                                                 end
 201                                         end # SM
 202                                         device pci 14.1 on end # IDE    0x438c
 203                                         device pci 14.2 on end # HDA    0x4383
 204                                         device pci 14.3 on # LPC        0x438d
 205                                                 chip superio/ite/it8712f
 206                                                         device pnp 2e.0 off #  Floppy
 207                                                                 io 0x60 = 0x3f0
 208                                                                 irq 0x70 = 6
 209                                                                 drq 0x74 = 2
 210                                                         end
 211                                                         device pnp 2e.1 on #  Com1
 212                                                                 io 0x60 = 0x3f8
 213                                                                 irq 0x70 = 4
 214                                                         end
 215                                                         device pnp 2e.2 on #  Com2
 216                                                                 io 0x60 = 0x2f8
 217                                                                 irq 0x70 = 3
 218                                                         end
 219                                                         device pnp 2e.3 on #  Parallel Port
 220                                                                 io 0x60 = 0x378
 221                                                                 irq 0x70 = 7
 222                                                         end
 223                                                         device pnp 2e.4 off end #  EC
 224                                                         device pnp 2e.5 on #  Keyboard
 225                                                                 io 0x60 = 0x60
 226                                                                 io 0x62 = 0x64
 227                                                                 irq 0x70 = 1
 228                                                         end
 229                                                         device pnp 2e.6 on #  Mouse
 230                                                                 irq 0x70 = 12
 231                                                         end
 232                                                         device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
 233                                                         end
 234                                                         device pnp 2e.8 off #  MIDI
 235                                                                 io 0x60 = 0x300
 236                                                                 irq 0x70 = 9
 237                                                         end
 238                                                         device pnp 2e.9 off #  GAME
 239                                                                 io 0x60 = 0x220
 240                                                         end
 241                                                         device pnp 2e.a off end #  CIR
 242                                                 end     #superio/ite/it8712f
 243                                         end             #LPC
 244                                         device pci 14.4 on end # PCI 0x4384
 245                                         device pci 14.5 on end # ACI 0x4382
 246                                         device pci 14.6 on end # MCI 0x438e
 247                                         register "ide0_enable" = "1"
 248                                         register "sata0_enable" = "1"
 249                                         register "hda_viddid" = "0x10ec0882"
 250                                 end     #southbridge/amd/sb600
 251                         end #  device pci 18.0
 252
 253                         device pci 18.0 on end
 254                         device pci 18.0 on end
 255                         device pci 18.1 on end
 256                         device pci 18.2 on end
 257                         device pci 18.3 on end
 258                 end             #northbridge/amd/amdk8
 259         end #pci_domain
 260 end             #northbridge/amd/amdk8/root_complex
 261