1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
8 static void *smp_write_config_table(void *v)
10 struct mp_config_table *mc;
12 unsigned char bus_pxhd_1;
13 unsigned char bus_pxhd_2;
14 unsigned char bus_pxhd_3;
15 unsigned char bus_pxhd_4;
16 unsigned char bus_ich5r_1;
18 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
20 mptable_init(mc, LAPIC_ADDR);
22 smp_write_processors(mc);
28 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
30 bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
33 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
38 dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
40 bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
44 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n");
49 dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
51 bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
55 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n");
61 dev = dev_find_slot(0, PCI_DEVFN(0x4,0));
63 bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
67 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n");
72 dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
74 bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
78 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n");
85 mptable_write_buses(mc, NULL, &bus_isa);
89 smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
94 dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
96 res = find_resource(dev, PCI_BASE_ADDRESS_0);
98 smp_write_ioapic(mc, 0x03, 0x20, res->base);
102 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
105 dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
107 res = find_resource(dev, PCI_BASE_ADDRESS_0);
109 smp_write_ioapic(mc, 0x04, 0x20, res->base);
113 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
116 mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
118 /* ISA backward compatibility interrupts */
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
120 0x00, 0x74, 0x02, 0x10);
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
122 0x00, 0x76, 0x02, 0x12);
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
124 0x00, 0x77, 0x02, 0x17);
125 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
126 0x00, 0x75, 0x02, 0x13);
127 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
128 0x00, 0x74, 0x02, 0x10);
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
130 0x00, 0x7c, 0x02, 0x12);
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
132 0x00, 0x7d, 0x02, 0x11);
133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
134 bus_pxhd_1, 0x08, 0x03, 0x00);
135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
136 bus_pxhd_1, 0x0c, 0x03, 0x06);
137 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
138 bus_pxhd_1, 0x0d, 0x03, 0x07);
139 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
140 bus_pxhd_2, 0x08, 0x04, 0x00);
141 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
142 bus_ich5r_1, 0x04, 0x02, 0x10);
143 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
144 bus_pxhd_4, 0x00, 0x02, 0x10);
146 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
147 (bus_isa - 1), 0x04, 0x02, 0x10);
149 /* Standard local interrupt assignments */
151 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
152 bus_isa, 0x00, MP_APIC_ALL, 0x00);
154 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
155 bus_isa, 0x00, MP_APIC_ALL, 0x01);
157 /* There is no extension information... */
159 /* Compute the checksums */
160 return mptable_finalize(mc);
163 unsigned long write_smp_table(unsigned long addr)
166 v = smp_write_floating_table(addr, 0);
167 return (unsigned long)smp_write_config_table(v);