src/mainboard/supermicro/x6dhr_ig2/mptable.c

   1 #include <console/console.h>
   2 #include <arch/smp/mpspec.h>
   3 #include <arch/ioapic.h>
   4 #include <device/pci.h>
   5 #include <string.h>
   6 #include <stdint.h>
   7
   8 static void *smp_write_config_table(void *v)
   9 {
  10         struct mp_config_table *mc;
  11         unsigned char bus_num;
  12         unsigned char bus_isa;
  13         unsigned char bus_pxhd_1;
  14         unsigned char bus_pxhd_2;
  15         unsigned char bus_pxhd_3;
  16         unsigned char bus_pxhd_4;
  17         unsigned char bus_ich5r_1;
  18
  19         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  20
  21         mptable_init(mc, "X6DHR-iG2   ", LAPIC_ADDR);
  22
  23         smp_write_processors(mc);
  24
  25         {
  26                 device_t dev;
  27
  28                 /* ich5r */
  29                 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
  30                 if (dev) {
  31                         bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  32                         bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
  33                         bus_isa++;
  34                 }
  35                 else {
  36                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
  37
  38                         bus_ich5r_1 = 7;
  39                         bus_isa = 8;
  40                 }
  41                 /* pxhd-1 */
  42                 dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
  43                 if (dev) {
  44                         bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  45
  46                 }
  47                 else {
  48                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n");
  49
  50                         bus_pxhd_1 = 2;
  51                 }
  52                 /* pxhd-2 */
  53                 dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
  54                 if (dev) {
  55                         bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  56
  57                 }
  58                 else {
  59                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n");
  60
  61                         bus_pxhd_2 = 3;
  62                 }
  63
  64                 /* pxhd-3 */
  65                 dev = dev_find_slot(0, PCI_DEVFN(0x4,0));
  66                 if (dev) {
  67                         bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  68
  69                 }
  70                 else {
  71                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n");
  72
  73                         bus_pxhd_3 = 5;
  74                 }
  75                 /* pxhd-4 */
  76                 dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
  77                 if (dev) {
  78                         bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  79
  80                 }
  81                 else {
  82                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n");
  83
  84                         bus_pxhd_4 = 6;
  85                 }
  86
  87         }
  88
  89         /* define bus and isa numbers */
  90         for(bus_num = 0; bus_num < bus_isa; bus_num++) {
  91                 smp_write_bus(mc, bus_num, "PCI   ");
  92         }
  93         smp_write_bus(mc, bus_isa, "ISA   ");
  94
  95         /* IOAPIC handling */
  96
  97         smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
  98         {
  99                 struct resource *res;
 100                 device_t dev;
 101                 /* pxhd apic 3 */
 102                 dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
 103                 if (dev) {
 104                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 105                         if (res) {
 106                                 smp_write_ioapic(mc, 0x03, 0x20, res->base);
 107                         }
 108                 }
 109                 else {
 110                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
 111                 }
 112                 /* pxhd apic 4 */
 113                 dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
 114                 if (dev) {
 115                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 116                         if (res) {
 117                                 smp_write_ioapic(mc, 0x04, 0x20, res->base);
 118                         }
 119                 }
 120                 else {
 121                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
 122                 }
 123         }
 124         mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
 125
 126         /* ISA backward compatibility interrupts  */
 127         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 128                 0x00, 0x74, 0x02, 0x10);
 129         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 130                 0x00, 0x76, 0x02, 0x12);
 131         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 132                 0x00, 0x77, 0x02, 0x17);
 133         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 134                 0x00, 0x75, 0x02, 0x13);
 135         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 136                 0x00, 0x74, 0x02, 0x10);
 137         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 138                 0x00, 0x7c, 0x02, 0x12);
 139         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 140                 0x00, 0x7d, 0x02, 0x11);
 141         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 142                 bus_pxhd_1, 0x08, 0x03, 0x00);
 143         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 144                 bus_pxhd_1, 0x0c, 0x03, 0x06);
 145         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 146                 bus_pxhd_1, 0x0d, 0x03, 0x07);
 147         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 148                 bus_pxhd_2, 0x08, 0x04, 0x00);
 149         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 150                 bus_ich5r_1, 0x04, 0x02, 0x10);
 151         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 152                 bus_pxhd_4, 0x00, 0x02, 0x10);
 153 #if 0
 154         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 155                 (bus_isa - 1), 0x04, 0x02, 0x10);
 156 #endif
 157         /* Standard local interrupt assignments */
 158 #if 0
 159         smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 160                 bus_isa, 0x00, MP_APIC_ALL, 0x00);
 161 #endif
 162         smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 163                 bus_isa, 0x00, MP_APIC_ALL, 0x01);
 164
 165         /* There is no extension information... */
 166
 167         /* Compute the checksums */
 168         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 169
 170         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 171         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 172                 mc, smp_next_mpe_entry(mc));
 173         return smp_next_mpe_entry(mc);
 174 }
 175
 176 unsigned long write_smp_table(unsigned long addr)
 177 {
 178         void *v;
 179         v = smp_write_floating_table(addr);
 180         return (unsigned long)smp_write_config_table(v);
 181 }
 182