src/mainboard/supermicro/x6dhr_ig2/Config.lb

   1 ##
   2 ## Only use the option table in a normal image
   3 ##
   4 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
   5
   6 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
   7 default CONFIG_XIP_ROM_SIZE = 64 * 1024
   8 include /config/nofailovercalculation.lb
   9
  10 ##
  11 ## Set all of the defaults for an x86 architecture
  12 ##
  13
  14 arch i386 end
  15
  16 ##
  17 ## Build the objects we have code for in this directory.
  18 ##
  19
  20 driver mainboard.o
  21 if CONFIG_GENERATE_MP_TABLE object mptable.o end
  22 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
  23 object reset.o
  24
  25 ##
  26 ## Romcc output
  27 ##
  28 makerule ./failover.E
  29         depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
  30         action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
  31 end
  32
  33 makerule ./failover.inc
  34         depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
  35         action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
  36 end
  37
  38 makerule ./auto.E
  39         depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
  40         action  "../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
  41 end
  42 makerule ./auto.inc
  43         depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
  44         action  "../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
  45 end
  46
  47 ##
  48 ## Build our 16 bit and 32 bit coreboot entry code
  49 ##
  50 mainboardinit cpu/x86/16bit/entry16.inc
  51 mainboardinit cpu/x86/32bit/entry32.inc
  52 ldscript /cpu/x86/16bit/entry16.lds
  53 ldscript /cpu/x86/32bit/entry32.lds
  54
  55 ##
  56 ## Build our reset vector (This is where coreboot is entered)
  57 ##
  58 if CONFIG_USE_FALLBACK_IMAGE
  59         mainboardinit cpu/x86/16bit/reset16.inc
  60         ldscript /cpu/x86/16bit/reset16.lds
  61 else
  62         mainboardinit cpu/x86/32bit/reset32.inc
  63         ldscript /cpu/x86/32bit/reset32.lds
  64 end
  65
  66 ### Should this be in the northbridge code?
  67 mainboardinit arch/i386/lib/cpu_reset.inc
  68
  69 ##
  70 ## Include an id string (For safe flashing)
  71 ##
  72 mainboardinit arch/i386/lib/id.inc
  73 ldscript /arch/i386/lib/id.lds
  74
  75 ###
  76 ### This is the early phase of coreboot startup
  77 ### Things are delicate and we test to see if we should
  78 ### failover to another image.
  79 ###
  80 if CONFIG_USE_FALLBACK_IMAGE
  81         ldscript /arch/i386/lib/failover.lds
  82         mainboardinit ./failover.inc
  83 end
  84
  85 ###
  86 ### O.k. We aren't just an intermediary anymore!
  87 ###
  88
  89 ##
  90 ## Setup RAM
  91 ##
  92 mainboardinit cpu/x86/fpu/enable_fpu.inc
  93 mainboardinit cpu/x86/mmx/enable_mmx.inc
  94 mainboardinit cpu/x86/sse/enable_sse.inc
  95 mainboardinit ./auto.inc
  96 mainboardinit cpu/x86/sse/disable_sse.inc
  97 mainboardinit cpu/x86/mmx/disable_mmx.inc
  98
  99 ##
 100 ## Include the secondary Configuration files
 101 ##
 102 dir /pc80
 103 config chip.h
 104
 105 chip northbridge/intel/e7520 # mch
 106         device pci_domain 0 on
 107                 chip southbridge/intel/i82801er # i82801er
 108                         # USB ports
 109                         device pci 1d.0 on end
 110                         device pci 1d.1 on end
 111                         device pci 1d.2 on end
 112                         device pci 1d.3 on end
 113                         device pci 1d.7 on end
 114
 115                         # -> Bridge
 116                         device pci 1e.0 on end
 117
 118                         # -> ISA
 119                         device pci 1f.0 on
 120                                 chip superio/winbond/w83627hf
 121                                         device pnp 2e.0 off end
 122                                         device pnp 2e.2 on
 123                                                  io 0x60 = 0x3f8
 124                                                 irq 0x70 = 4
 125                                         end
 126                                         device pnp 2e.3 on
 127                                                  io 0x60 = 0x2f8
 128                                                 irq 0x70 = 3
 129                                         end
 130                                         device pnp 2e.4 off end
 131                                         device pnp 2e.5 off end
 132                                         device pnp 2e.6 off end
 133                                         device pnp 2e.7 off end
 134                                         device pnp 2e.9 off end
 135                                         device pnp 2e.a on  end
 136                                         device pnp 2e.b off end
 137                                 end
 138                         end
 139                         # -> IDE
 140                         device pci 1f.1 on end
 141                         # -> SATA
 142                         device pci 1f.2 on end
 143                         device pci 1f.3 on end
 144
 145                         register "pirq_a_d" = "0x0b070a05"
 146                         register "pirq_e_h" = "0x0a808080"
 147                 end
 148                 device pci 00.0 on end
 149                 device pci 00.1 on end
 150                 device pci 01.0 on end
 151                 device pci 02.0 on
 152                         chip southbridge/intel/pxhd # pxhd1
 153                                 # Bus bridges and ioapics usually bus 1
 154                                 device pci 0.0 on
 155                                 # On board gig e1000
 156                                         chip drivers/generic/generic
 157                                                 device pci 03.0 on end
 158                                                 device pci 03.1 on end
 159                                         end
 160                                 end
 161                                 device pci 0.1 on end
 162                                 device pci 0.2 on end
 163                                 device pci 0.3 on end
 164                         end
 165                 end
 166                 device pci 04.0 on end
 167                 device pci 06.0 on end
 168         end
 169         device apic_cluster 0 on
 170                 chip cpu/intel/socket_mPGA604 # cpu 0
 171                         device apic 0 on end
 172                 end
 173                 chip cpu/intel/socket_mPGA604 # cpu 1
 174                         device apic 6 on end
 175                 end
 176         end
 177         register "intrline" = "0x00070105"
 178 end
 179