1 #include <device/pnp_def.h>
3 #define NSC_WD_DEV PNP_DEV(0x2e, 0xa)
4 #define NSC_WDBASE 0x600
5 #define ICH5_WDBASE 0x400
6 #define ICH5_GPIOBASE 0x500
8 static void disable_sio_watchdog(device_t dev)
11 /* FIXME move me somewhere more appropriate */
12 pnp_set_logical_device(dev);
13 pnp_set_enable(dev, 1);
14 pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE);
15 /* disable the sio watchdog */
16 outb(0, NSC_WDBASE + 0);
17 pnp_set_enable(dev, 0);
21 static void disable_ich5_watchdog(void)
23 /* FIXME move me somewhere more appropriate */
25 unsigned long value, base;
26 dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
27 if (dev == PCI_DEV_INVALID) {
30 /* Enable I/O space */
31 value = pci_read_config16(dev, 0x04);
33 pci_write_config16(dev, 0x04, value);
35 /* Set and enable acpibase */
36 pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
37 pci_write_config8(dev, 0x44, 0x10);
38 base = ICH5_WDBASE + 0x60;
40 /* Set bit 11 in TCO1_CNT */
41 value = inw(base + 0x08);
43 outw(value, base + 0x08);
45 /* Clear TCO timeout status */
46 outw(0x0008, base + 0x04);
47 outw(0x0002, base + 0x06);
50 static void disable_jarell_frb3(void)
54 unsigned long value, base;
55 dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
56 if (dev == PCI_DEV_INVALID) {
59 /* Enable I/O space */
60 value = pci_read_config16(dev, 0x04);
62 pci_write_config16(dev, 0x04, value);
65 pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1);
69 value = pci_read_config32(dev, 0x5c);
71 pci_write_config32(dev, 0x5c, value);
73 /* Configure GPIO 48 and 40 as GPIO */
74 value = inl(base + 0x30);
75 value |= (1 << 16) | ( 1 << 8);
76 outl(value, base + 0x30);
78 /* Configure GPIO 48 as Output */
79 value = inl(base + 0x34);
81 outl(value, base + 0x34);
83 /* Toggle GPIO 48 high to low */
84 value = inl(base + 0x38);
86 outl(value, base + 0x38);
88 outl(value, base + 0x38);
92 static void disable_watchdogs(void)
94 // disable_sio_watchdog(NSC_WD_DEV);
95 disable_ich5_watchdog();
96 // disable_jarell_frb3();
97 print_debug("Watchdogs disabled\n");