src/mainboard/supermicro/x6dhr_ig/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "lib/ramtest.c"
  10 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  11 #include "northbridge/intel/e7520/raminit.h"
  12 #include "superio/winbond/w83627hf/w83627hf.h"
  13 #include "cpu/x86/lapic/boot_cpu.c"
  14 #include "cpu/x86/mtrr/earlymtrr.c"
  15 #include "debug.c"
  16 #include "watchdog.c"
  17 #include "reset.c"
  18 #include "x6dhr_fixups.c"
  19 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  20 #include "northbridge/intel/e7520/memory_initialized.c"
  21 #include "cpu/x86/bist.h"
  22
  23 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  24 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
  25
  26 #define DEVPRES_CONFIG  ( \
  27         DEVPRES_D0F0 | \
  28         DEVPRES_D1F0 | \
  29         DEVPRES_D2F0 | \
  30         DEVPRES_D3F0 | \
  31         DEVPRES_D4F0 | \
  32         DEVPRES_D6F0 | \
  33         0 )
  34 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  35
  36 static inline int spd_read_byte(unsigned device, unsigned address)
  37 {
  38         return smbus_read_byte(device, address);
  39 }
  40
  41 #include "northbridge/intel/e7520/raminit.c"
  42 #include "lib/generic_sdram.c"
  43 #include "arch/i386/lib/stages.c"
  44
  45 static void main(unsigned long bist)
  46 {
  47         /*
  48          *
  49          *
  50          */
  51         static const struct mem_controller mch[] = {
  52                 {
  53                         .node_id = 0,
  54                         /*
  55                         .f0 = PCI_DEV(0, 0x00, 0),
  56                         .f1 = PCI_DEV(0, 0x00, 1),
  57                         .f2 = PCI_DEV(0, 0x00, 2),
  58                         .f3 = PCI_DEV(0, 0x00, 3),
  59                         */
  60                         .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
  61                         .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
  62                 }
  63         };
  64
  65         if (bist == 0) {
  66                 /* Skip this if there was a built in self test failure */
  67                 early_mtrr_init();
  68                 if (memory_initialized()) {
  69                         skip_romstage();
  70                 }
  71         }
  72         /* Setup the console */
  73         outb(0x87,0x2e);
  74         outb(0x87,0x2e);
  75         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
  76         w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  77         uart_init();
  78         console_init();
  79
  80         /* Halt if there was a built in self test failure */
  81 //      report_bist_failure(bist);
  82
  83         /* MOVE ME TO A BETTER LOCATION !!! */
  84         /* config LPC decode for flash memory access */
  85         device_t dev;
  86         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
  87         if (dev == PCI_DEV_INVALID) {
  88                 die("Missing ich5?");
  89         }
  90         pci_write_config32(dev, 0xe8, 0x00000000);
  91         pci_write_config8(dev, 0xf0, 0x00);
  92
  93 #if 0
  94         display_cpuid_update_microcode();
  95 #endif
  96 #if 0
  97         print_pci_devices();
  98 #endif
  99 #if 1
 100         enable_smbus();
 101 #endif
 102 #if 0
 103 //      dump_spd_registers(&cpu[0]);
 104         int i;
 105         for(i = 0; i < 1; i++) {
 106                 dump_spd_registers();
 107         }
 108 #endif
 109         disable_watchdogs();
 110 //      dump_ipmi_registers();
 111         mainboard_set_e7520_leds();
 112         sdram_initialize(ARRAY_SIZE(mch), mch);
 113 #if 1
 114         dump_pci_devices();
 115 #endif
 116 #if 0
 117         dump_pci_device(PCI_DEV(0, 0x00, 0));
 118         dump_bar14(PCI_DEV(0, 0x00, 0));
 119 #endif
 120
 121 #if 0 // temporarily disabled
 122         /* Check the first 1M */
 123 //      ram_check(0x00000000, 0x000100000);
 124 //      ram_check(0x00000000, 0x000a0000);
 125 //      ram_check(0x00100000, 0x01000000);
 126         ram_check(0x00100000, 0x00100100);
 127         /* check the first 1M in the 3rd Gig */
 128 //      ram_check(0x30100000, 0x31000000);
 129 #endif
 130 #if 0
 131         ram_check(0x00000000, 0x02000000);
 132 #endif
 133
 134 #if 0
 135         while(1) {
 136                 hlt();
 137         }
 138 #endif
 139 }
 140