src/mainboard/supermicro/x6dhr_ig/mptable.c

   1 #include <console/console.h>
   2 #include <arch/smp/mpspec.h>
   3 #include <arch/ioapic.h>
   4 #include <device/pci.h>
   5 #include <string.h>
   6 #include <stdint.h>
   7
   8 static void *smp_write_config_table(void *v)
   9 {
  10         static const char sig[4] = "PCMP";
  11         static const char oem[8] = "COREBOOT";
  12         static const char productid[12] = "X6DHR-iG    ";
  13         struct mp_config_table *mc;
  14         unsigned char bus_num;
  15         unsigned char bus_isa;
  16         unsigned char bus_pxhd_1;
  17         unsigned char bus_pxhd_2;
  18         unsigned char bus_pxhd_3;
  19         unsigned char bus_pxhd_4;
  20         unsigned char bus_ich5r_1;
  21
  22         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  23         memset(mc, 0, sizeof(*mc));
  24
  25         memcpy(mc->mpc_signature, sig, sizeof(sig));
  26         mc->mpc_length = sizeof(*mc); /* initially just the header */
  27         mc->mpc_spec = 0x04;
  28         mc->mpc_checksum = 0; /* not yet computed */
  29         memcpy(mc->mpc_oem, oem, sizeof(oem));
  30         memcpy(mc->mpc_productid, productid, sizeof(productid));
  31         mc->mpc_oemptr = 0;
  32         mc->mpc_oemsize = 0;
  33         mc->mpc_entry_count = 0; /* No entries yet... */
  34         mc->mpc_lapic = LAPIC_ADDR;
  35         mc->mpe_length = 0;
  36         mc->mpe_checksum = 0;
  37         mc->reserved = 0;
  38
  39         smp_write_processors(mc);
  40
  41         {
  42                 device_t dev;
  43
  44                 /* ich5r */
  45                 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
  46                 if (dev) {
  47                         bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  48                         bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
  49                         bus_isa++;
  50                 }
  51                 else {
  52                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n");
  53
  54                         bus_ich5r_1 = 9;
  55                         bus_isa = 10;
  56                 }
  57                 /* pxhd-1 */
  58                 dev = dev_find_slot(2, PCI_DEVFN(0x0,0));
  59                 if (dev) {
  60                         bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  61
  62                 }
  63                 else {
  64                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
  65
  66                         bus_pxhd_1 = 3;
  67                 }
  68                 /* pxhd-2 */
  69                 dev = dev_find_slot(2, PCI_DEVFN(0x00,2));
  70                 if (dev) {
  71                         bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  72
  73                 }
  74                 else {
  75                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
  76
  77                         bus_pxhd_2 = 4;
  78                 }
  79
  80                 /* pxhd-3 */
  81                 dev = dev_find_slot(5, PCI_DEVFN(0x0,0));
  82                 if (dev) {
  83                         bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  84
  85                 }
  86                 else {
  87                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
  88
  89                         bus_pxhd_3 = 6;
  90                 }
  91                 /* pxhd-4 */
  92                 dev = dev_find_slot(5, PCI_DEVFN(0x00,2));
  93                 if (dev) {
  94                         bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  95
  96                 }
  97                 else {
  98                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
  99
 100                         bus_pxhd_4 = 7;
 101                 }
 102
 103         }
 104
 105         /* define bus and isa numbers */
 106         for(bus_num = 0; bus_num < bus_isa; bus_num++) {
 107                 smp_write_bus(mc, bus_num, "PCI   ");
 108         }
 109         smp_write_bus(mc, bus_isa, "ISA   ");
 110
 111         /* IOAPIC handling */
 112
 113         smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
 114         {
 115                 struct resource *res;
 116                 device_t dev;
 117                 /* pxhd apic 3 */
 118                 dev = dev_find_slot(2, PCI_DEVFN(0x00,1));
 119                 if (dev) {
 120                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 121                         if (res) {
 122                                 smp_write_ioapic(mc, 0x03, 0x20, res->base);
 123                         }
 124                 }
 125                 else {
 126                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 2:00.1\n");
 127                 }
 128                 /* pxhd apic 4 */
 129                 dev = dev_find_slot(2, PCI_DEVFN(0x00,3));
 130                 if (dev) {
 131                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 132                         if (res) {
 133                                 smp_write_ioapic(mc, 0x04, 0x20, res->base);
 134                         }
 135                 }
 136                 else {
 137                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 2:00.3\n");
 138                 }
 139                 /* pxhd apic 5 */
 140                 dev = dev_find_slot(5, PCI_DEVFN(0x00,1));
 141                 if (dev) {
 142                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 143                         if (res) {
 144                                 smp_write_ioapic(mc, 0x05, 0x20, res->base);
 145                         }
 146                 }
 147                 else {
 148                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 5:00.1\n");
 149                 }
 150                 /* pxhd apic 8 */
 151                 dev = dev_find_slot(5, PCI_DEVFN(0x00,3));
 152                 if (dev) {
 153                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 154                         if (res) {
 155                                 smp_write_ioapic(mc, 0x08, 0x20, res->base);
 156                         }
 157                 }
 158                 else {
 159                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 5:00.3\n");
 160                 }
 161         }
 162
 163         mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
 164
 165         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 166                 0x00, 0x74, 0x02, 0x10);
 167         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 168                 0x00, 0x76, 0x02, 0x12);
 169         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 170                 0x00, 0x77, 0x02, 0x17);
 171         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 172                 0x00, 0x75, 0x02, 0x13);
 173         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 174                 0x00, 0x74, 0x02, 0x10);
 175         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 176                 0x00, 0x7c, 0x02, 0x12);
 177         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 178                 0x00, 0x7d, 0x02, 0x11);
 179         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 180                 bus_pxhd_2, 0x08, 0x04, 0x06);
 181         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 182                 bus_pxhd_2, 0x09, 0x04, 0x07);
 183         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 184                 bus_pxhd_3, 0x08, 0x05, 0x00);
 185         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 186                 bus_pxhd_4, 0x08, 0x08, 0x00);
 187         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 188                 (bus_isa - 1), 0x04, 0x02, 0x10);
 189
 190         /* Standard local interrupt assignments */
 191         smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 192                 bus_isa, 0x00, MP_APIC_ALL, 0x00);
 193         smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 194                 bus_isa, 0x00, MP_APIC_ALL, 0x01);
 195
 196         /* There is no extension information... */
 197
 198         /* Compute the checksums */
 199         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 200
 201         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 202         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 203                 mc, smp_next_mpe_entry(mc));
 204         return smp_next_mpe_entry(mc);
 205 }
 206
 207 unsigned long write_smp_table(unsigned long addr)
 208 {
 209         void *v;
 210         v = smp_write_floating_table(addr);
 211         return (unsigned long)smp_write_config_table(v);
 212 }
 213