src/mainboard/supermicro/x6dhr_ig/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <stdlib.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "ram/ramtest.c"
  14 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
  15 #include "northbridge/intel/e7520/raminit.h"
  16 #include "superio/winbond/w83627hf/w83627hf.h"
  17 #include "cpu/x86/lapic/boot_cpu.c"
  18 #include "cpu/x86/mtrr/earlymtrr.c"
  19 #include "debug.c"
  20 #include "watchdog.c"
  21 #include "reset.c"
  22 #include "x6dhr_fixups.c"
  23 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  24 #include "northbridge/intel/e7520/memory_initialized.c"
  25 #include "cpu/x86/bist.h"
  26
  27
  28 #define SIO_GPIO_BASE 0x680
  29 #define SIO_XBUS_BASE 0x4880
  30
  31 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  32 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
  33
  34 #define DEVPRES_CONFIG  ( \
  35         DEVPRES_D0F0 | \
  36         DEVPRES_D1F0 | \
  37         DEVPRES_D2F0 | \
  38         DEVPRES_D3F0 | \
  39         DEVPRES_D4F0 | \
  40         DEVPRES_D6F0 | \
  41         0 )
  42 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  43
  44 #define RECVENA_CONFIG  0x0808090a
  45 #define RECVENB_CONFIG  0x0808090a
  46
  47 //void udelay(int usecs)
  48 //{
  49 //        int i;
  50 //        for(i = 0; i < usecs; i++)
  51 //                outb(i&0xff, 0x80);
  52 //}
  53
  54 #if 0
  55 static void hard_reset(void)
  56 {
  57         /* enable cf9 */
  58         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  59         /* reset */
  60         outb(0x0e, 0x0cf9);
  61 }
  62 #endif
  63
  64 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  65 {
  66         /* nothing to do */
  67 }
  68 static inline int spd_read_byte(unsigned device, unsigned address)
  69 {
  70         return smbus_read_byte(device, address);
  71 }
  72
  73 #include "northbridge/intel/e7520/raminit.c"
  74 #include "sdram/generic_sdram.c"
  75
  76
  77 static void main(unsigned long bist)
  78 {
  79         /*
  80          *
  81          *
  82          */
  83         static const struct mem_controller mch[] = {
  84                 {
  85                         .node_id = 0,
  86                         .f0 = PCI_DEV(0, 0x00, 0),
  87                         .f1 = PCI_DEV(0, 0x00, 1),
  88                         .f2 = PCI_DEV(0, 0x00, 2),
  89                         .f3 = PCI_DEV(0, 0x00, 3),
  90                         .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
  91                         .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
  92                 }
  93         };
  94
  95         if (bist == 0) {
  96                 /* Skip this if there was a built in self test failure */
  97                 early_mtrr_init();
  98                 if (memory_initialized()) {
  99                         asm volatile ("jmp __cpu_reset");
 100                 }
 101         }
 102         /* Setup the console */
 103         outb(0x87,0x2e);
 104         outb(0x87,0x2e);
 105         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
 106         w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE);
 107         uart_init();
 108         console_init();
 109
 110         /* Halt if there was a built in self test failure */
 111 //      report_bist_failure(bist);
 112
 113         /* MOVE ME TO A BETTER LOCATION !!! */
 114         /* config LPC decode for flash memory access */
 115         device_t dev;
 116         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
 117         if (dev == PCI_DEV_INVALID) {
 118                 die("Missing ich5?");
 119         }
 120         pci_write_config32(dev, 0xe8, 0x00000000);
 121         pci_write_config8(dev, 0xf0, 0x00);
 122
 123 #if 0
 124         display_cpuid_update_microcode();
 125 #endif
 126 #if 0
 127         print_pci_devices();
 128 #endif
 129 #if 1
 130         enable_smbus();
 131 #endif
 132 #if 0
 133 //      dump_spd_registers(&cpu[0]);
 134         int i;
 135         for(i = 0; i < 1; i++) {
 136                 dump_spd_registers();
 137         }
 138 #endif
 139         disable_watchdogs();
 140 //      dump_ipmi_registers();
 141         mainboard_set_e7520_leds();
 142 //      memreset_setup();
 143         sdram_initialize(ARRAY_SIZE(mch), mch);
 144 #if 1
 145         dump_pci_devices();
 146 #endif
 147 #if 0
 148         dump_pci_device(PCI_DEV(0, 0x00, 0));
 149         dump_bar14(PCI_DEV(0, 0x00, 0));
 150 #endif
 151
 152 #if 0 // temporarily disabled
 153         /* Check the first 1M */
 154 //      ram_check(0x00000000, 0x000100000);
 155 //      ram_check(0x00000000, 0x000a0000);
 156 //      ram_check(0x00100000, 0x01000000);
 157         ram_check(0x00100000, 0x00100100);
 158         /* check the first 1M in the 3rd Gig */
 159 //      ram_check(0x30100000, 0x31000000);
 160 #endif
 161 #if 0
 162         ram_check(0x00000000, 0x02000000);
 163 #endif
 164
 165 #if 0
 166         while(1) {
 167                 hlt();
 168         }
 169 #endif
 170 }