2 ## Only use the option table in a normal image
4 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
6 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
7 default CONFIG_XIP_ROM_SIZE = 64 * 1024
8 include /config/nofailovercalculation.lb
11 ## Set all of the defaults for an x86 architecture
17 ## Build the objects we have code for in this directory.
21 if CONFIG_GENERATE_MP_TABLE object mptable.o end
22 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
29 depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
30 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
33 makerule ./failover.inc
34 depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
35 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
39 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
40 action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
43 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
44 action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
48 ## Build our 16 bit and 32 bit coreboot entry code
50 mainboardinit cpu/x86/16bit/entry16.inc
51 mainboardinit cpu/x86/32bit/entry32.inc
52 ldscript /cpu/x86/16bit/entry16.lds
53 ldscript /cpu/x86/32bit/entry32.lds
56 ## Build our reset vector (This is where coreboot is entered)
58 if CONFIG_USE_FALLBACK_IMAGE
59 mainboardinit cpu/x86/16bit/reset16.inc
60 ldscript /cpu/x86/16bit/reset16.lds
62 mainboardinit cpu/x86/32bit/reset32.inc
63 ldscript /cpu/x86/32bit/reset32.lds
66 ### Should this be in the northbridge code?
67 mainboardinit arch/i386/lib/cpu_reset.inc
70 ## Include an id string (For safe flashing)
72 mainboardinit arch/i386/lib/id.inc
73 ldscript /arch/i386/lib/id.lds
76 ### This is the early phase of coreboot startup
77 ### Things are delicate and we test to see if we should
78 ### failover to another image.
80 if CONFIG_USE_FALLBACK_IMAGE
81 ldscript /arch/i386/lib/failover.lds
82 mainboardinit ./failover.inc
86 ### O.k. We aren't just an intermediary anymore!
92 mainboardinit cpu/x86/fpu/enable_fpu.inc
93 mainboardinit cpu/x86/sse/enable_sse.inc
94 mainboardinit ./auto.inc
95 mainboardinit cpu/x86/sse/disable_sse.inc
96 mainboardinit cpu/x86/mmx/disable_mmx.inc
99 ## Include the secondary Configuration files
104 chip northbridge/intel/e7520 # mch
105 device pci_domain 0 on
106 chip southbridge/intel/i82801er # i82801er
108 device pci 1d.0 on end
109 device pci 1d.1 on end
110 device pci 1d.2 on end
111 device pci 1d.3 on end
112 device pci 1d.7 on end
115 device pci 1e.0 on end
119 chip superio/winbond/w83627hf
120 device pnp 2e.0 off end
129 device pnp 2e.4 off end
130 device pnp 2e.5 off end
131 device pnp 2e.6 off end
132 device pnp 2e.7 off end
133 device pnp 2e.9 off end
134 device pnp 2e.a on end
135 device pnp 2e.b off end
138 device pci 1f.1 on end
139 device pci 1f.2 on end
140 device pci 1f.3 on end
142 register "pirq_a_d" = "0x0b070a05"
143 register "pirq_e_h" = "0x0a808080"
145 device pci 00.0 on end
146 device pci 00.1 on end
147 device pci 01.0 on end
148 device pci 02.0 on end
150 chip southbridge/intel/pxhd # pxhd1
151 # Bus bridges and ioapics usually bus 2
152 device pci 0.0 on end
153 device pci 0.1 on end
156 chip drivers/generic/generic
157 device pci 02.0 on end
158 device pci 02.1 on end
161 device pci 0.3 on end
165 chip southbridge/intel/pxhd # pxhd2
166 # Bus bridges and ioapics usually bus 5
167 device pci 0.0 on end
168 # Slot 6 is usually 6:2.0
169 device pci 0.1 on end
170 device pci 0.2 on end
171 # Slot 7 is usually 7:2.0
172 device pci 0.3 on end
175 device pci 06.0 on end
177 device apic_cluster 0 on
178 chip cpu/intel/socket_mPGA604 # cpu 0
181 chip cpu/intel/socket_mPGA604 # cpu 1
185 register "intrline" = "0x00070105"