src/mainboard/supermicro/x6dhe_g2/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include "option_table.h"
   9 #include "pc80/mc146818rtc_early.c"
  10 #include "pc80/serial.c"
  11 #include "console/console.c"
  12 #include "lib/ramtest.c"
  13 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  14 #include "northbridge/intel/e7520/raminit.h"
  15 #include "superio/nsc/pc87427/pc87427.h"
  16 #include "cpu/x86/lapic/boot_cpu.c"
  17 #include "cpu/x86/mtrr/earlymtrr.c"
  18 #include "debug.c"
  19 #include "watchdog.c"
  20 #include "reset.c"
  21 #include "x6dhe_g2_fixups.c"
  22 #include "superio/nsc/pc87427/pc87427_early_init.c"
  23 #include "northbridge/intel/e7520/memory_initialized.c"
  24 #include "cpu/x86/bist.h"
  25
  26 #define SIO_GPIO_BASE 0x680
  27 #define SIO_XBUS_BASE 0x4880
  28
  29 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1)
  30 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, PC87427_SP2)
  31
  32 #define DEVPRES_CONFIG  ( \
  33         DEVPRES_D1F0 | \
  34         DEVPRES_D2F0 | \
  35         DEVPRES_D3F0 | \
  36         DEVPRES_D4F0 | \
  37         DEVPRES_D6F0 | \
  38         0 )
  39 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  40
  41 #define RECVENA_CONFIG  0x0708090a
  42 #define RECVENB_CONFIG  0x0708090a
  43
  44 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  45 {
  46         /* nothing to do */
  47 }
  48 static inline int spd_read_byte(unsigned device, unsigned address)
  49 {
  50         return smbus_read_byte(device, address);
  51 }
  52
  53 #include "northbridge/intel/e7520/raminit.c"
  54 #include "lib/generic_sdram.c"
  55 #include "arch/i386/lib/stages.c"
  56
  57 static void main(unsigned long bist)
  58 {
  59         /*
  60          *
  61          *
  62          */
  63         static const struct mem_controller mch[] = {
  64                 {
  65                         .node_id = 0,
  66                         /*
  67                         .f0 = PCI_DEV(0, 0x00, 0),
  68                         .f1 = PCI_DEV(0, 0x00, 1),
  69                         .f2 = PCI_DEV(0, 0x00, 2),
  70                         .f3 = PCI_DEV(0, 0x00, 3),
  71                         */
  72                         .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
  73                         .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
  74
  75                 }
  76         };
  77
  78         if (bist == 0) {
  79                 /* Skip this if there was a built in self test failure */
  80                 early_mtrr_init();
  81                 if (memory_initialized()) {
  82                         skip_romstage();
  83                 }
  84         }
  85         /* Setup the console */
  86         outb(0x87,0x2e);
  87         outb(0x87,0x2e);
  88         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
  89         pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  90         uart_init();
  91         console_init();
  92
  93         /* Halt if there was a built in self test failure */
  94 //      report_bist_failure(bist);
  95
  96         /* MOVE ME TO A BETTER LOCATION !!! */
  97         /* config LPC decode for flash memory access */
  98         device_t dev;
  99         dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
 100         if (dev == PCI_DEV_INVALID) {
 101                 die("Missing ich5r?");
 102         }
 103         pci_write_config32(dev, 0xe8, 0x00000000);
 104         pci_write_config8(dev, 0xf0, 0x00);
 105
 106 #if 0
 107         display_cpuid_update_microcode();
 108 #endif
 109 #if 0
 110         print_pci_devices();
 111 #endif
 112 #if 1
 113         enable_smbus();
 114 #endif
 115 #if 0
 116 //      dump_spd_registers(&cpu[0]);
 117         int i;
 118         for(i = 0; i < 1; i++) {
 119                 dump_spd_registers();
 120         }
 121 #endif
 122         disable_watchdogs();
 123 //      dump_ipmi_registers();
 124 //      mainboard_set_e7520_leds();
 125 //      memreset_setup();
 126         sdram_initialize(ARRAY_SIZE(mch), mch);
 127 #if 0
 128         dump_pci_devices();
 129 #endif
 130 #if 1
 131         dump_pci_device(PCI_DEV(0, 0x00, 0));
 132         //dump_bar14(PCI_DEV(0, 0x00, 0));
 133 #endif
 134
 135 #if 0 // temporarily disabled
 136         /* Check the first 1M */
 137 //      ram_check(0x00000000, 0x000100000);
 138 //      ram_check(0x00000000, 0x000a0000);
 139         ram_check(0x00100000, 0x01000000);
 140         /* check the first 1M in the 3rd Gig */
 141         ram_check(0x30100000, 0x31000000);
 142 #endif
 143 #if 0
 144         ram_check(0x00000000, 0x02000000);
 145 #endif
 146
 147 #if 0
 148         while(1) {
 149                 hlt();
 150         }
 151 #endif
 152 }
 153