src/mainboard/supermicro/x6dhe_g2/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  10 #include "northbridge/intel/e7520/raminit.h"
  11 #include "superio/nsc/pc87427/pc87427.h"
  12 #include "cpu/x86/lapic/boot_cpu.c"
  13 #include "cpu/x86/mtrr/earlymtrr.c"
  14 #include "debug.c"
  15 #include "watchdog.c"
  16 #include "reset.c"
  17 #include "x6dhe_g2_fixups.c"
  18 #include "superio/nsc/pc87427/pc87427_early_init.c"
  19 #include "northbridge/intel/e7520/memory_initialized.c"
  20 #include "cpu/x86/bist.h"
  21 #include <spd.h>
  22
  23 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1)
  24 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, PC87427_SP2)
  25
  26 #define DEVPRES_CONFIG  ( \
  27         DEVPRES_D1F0 | \
  28         DEVPRES_D2F0 | \
  29         DEVPRES_D3F0 | \
  30         DEVPRES_D4F0 | \
  31         DEVPRES_D6F0 | \
  32         0 )
  33 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  34
  35 static inline int spd_read_byte(unsigned device, unsigned address)
  36 {
  37         return smbus_read_byte(device, address);
  38 }
  39
  40 #include "northbridge/intel/e7520/raminit.c"
  41 #include "lib/generic_sdram.c"
  42 #include "arch/i386/lib/stages.c"
  43
  44 static void main(unsigned long bist)
  45 {
  46         static const struct mem_controller mch[] = {
  47                 {
  48                         .node_id = 0,
  49                         .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
  50                         .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
  51                 }
  52         };
  53
  54         if (bist == 0) {
  55                 /* Skip this if there was a built in self test failure */
  56                 early_mtrr_init();
  57                 if (memory_initialized())
  58                         skip_romstage();
  59         }
  60
  61         /* Setup the console */
  62         outb(0x87,0x2e);
  63         outb(0x87,0x2e);
  64         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
  65         pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  66         uart_init();
  67         console_init();
  68
  69         /* Halt if there was a built in self test failure */
  70 //      report_bist_failure(bist);
  71
  72         /* MOVE ME TO A BETTER LOCATION !!! */
  73         /* config LPC decode for flash memory access */
  74         device_t dev;
  75         dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
  76         if (dev == PCI_DEV_INVALID)
  77                 die("Missing ich5r?");
  78         pci_write_config32(dev, 0xe8, 0x00000000);
  79         pci_write_config8(dev, 0xf0, 0x00);
  80
  81 #if 0
  82         display_cpuid_update_microcode();
  83         print_pci_devices();
  84 #endif
  85 #if 1
  86         enable_smbus();
  87 #endif
  88 #if 0
  89 //      dump_spd_registers(&cpu[0]);
  90         int i;
  91         for(i = 0; i < 1; i++)
  92                 dump_spd_registers();
  93 #endif
  94         disable_watchdogs();
  95 //      dump_ipmi_registers();
  96 //      mainboard_set_e7520_leds();
  97         sdram_initialize(ARRAY_SIZE(mch), mch);
  98 #if 0
  99         dump_pci_devices();
 100 #endif
 101 #if 1
 102         dump_pci_device(PCI_DEV(0, 0x00, 0));
 103         //dump_bar14(PCI_DEV(0, 0x00, 0));
 104 #endif
 105 }