src/mainboard/supermicro/x6dhe_g2/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <stdlib.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "lib/ramtest.c"
  15 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  16 #include "northbridge/intel/e7520/raminit.h"
  17 #include "superio/nsc/pc87427/pc87427.h"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "cpu/x86/mtrr/earlymtrr.c"
  20 #include "debug.c"
  21 #include "watchdog.c"
  22 #include "reset.c"
  23 #include "x6dhe_g2_fixups.c"
  24 #include "superio/nsc/pc87427/pc87427_early_init.c"
  25 #include "northbridge/intel/e7520/memory_initialized.c"
  26 #include "cpu/x86/bist.h"
  27
  28
  29 #define SIO_GPIO_BASE 0x680
  30 #define SIO_XBUS_BASE 0x4880
  31
  32 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1)
  33 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, PC87427_SP2)
  34
  35 #define DEVPRES_CONFIG  ( \
  36         DEVPRES_D1F0 | \
  37         DEVPRES_D2F0 | \
  38         DEVPRES_D3F0 | \
  39         DEVPRES_D4F0 | \
  40         DEVPRES_D6F0 | \
  41         0 )
  42 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  43
  44 #define RECVENA_CONFIG  0x0708090a
  45 #define RECVENB_CONFIG  0x0708090a
  46
  47 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  48 {
  49         /* nothing to do */
  50 }
  51 static inline int spd_read_byte(unsigned device, unsigned address)
  52 {
  53         return smbus_read_byte(device, address);
  54 }
  55
  56 #include "northbridge/intel/e7520/raminit.c"
  57 #include "lib/generic_sdram.c"
  58
  59
  60 static void main(unsigned long bist)
  61 {
  62         /*
  63          *
  64          *
  65          */
  66         static const struct mem_controller mch[] = {
  67                 {
  68                         .node_id = 0,
  69                         .f0 = PCI_DEV(0, 0x00, 0),
  70                         .f1 = PCI_DEV(0, 0x00, 1),
  71                         .f2 = PCI_DEV(0, 0x00, 2),
  72                         .f3 = PCI_DEV(0, 0x00, 3),
  73                         .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
  74                         .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
  75
  76                 }
  77         };
  78
  79         if (bist == 0) {
  80                 /* Skip this if there was a built in self test failure */
  81                 early_mtrr_init();
  82                 if (memory_initialized()) {
  83                         asm volatile ("jmp __cpu_reset");
  84                 }
  85         }
  86         /* Setup the console */
  87         outb(0x87,0x2e);
  88         outb(0x87,0x2e);
  89         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
  90         pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  91         uart_init();
  92         console_init();
  93
  94         /* Halt if there was a built in self test failure */
  95 //      report_bist_failure(bist);
  96
  97         /* MOVE ME TO A BETTER LOCATION !!! */
  98         /* config LPC decode for flash memory access */
  99         device_t dev;
 100         dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
 101         if (dev == PCI_DEV_INVALID) {
 102                 die("Missing ich5r?");
 103         }
 104         pci_write_config32(dev, 0xe8, 0x00000000);
 105         pci_write_config8(dev, 0xf0, 0x00);
 106
 107 #if 0
 108         display_cpuid_update_microcode();
 109 #endif
 110 #if 0
 111         print_pci_devices();
 112 #endif
 113 #if 1
 114         enable_smbus();
 115 #endif
 116 #if 0
 117 //      dump_spd_registers(&cpu[0]);
 118         int i;
 119         for(i = 0; i < 1; i++) {
 120                 dump_spd_registers();
 121         }
 122 #endif
 123         disable_watchdogs();
 124 //      dump_ipmi_registers();
 125 //      mainboard_set_e7520_leds();
 126 //      memreset_setup();
 127         sdram_initialize(ARRAY_SIZE(mch), mch);
 128 #if 0
 129         dump_pci_devices();
 130 #endif
 131 #if 1
 132         dump_pci_device(PCI_DEV(0, 0x00, 0));
 133         //dump_bar14(PCI_DEV(0, 0x00, 0));
 134 #endif
 135
 136 #if 0 // temporarily disabled
 137         /* Check the first 1M */
 138 //      ram_check(0x00000000, 0x000100000);
 139 //      ram_check(0x00000000, 0x000a0000);
 140         ram_check(0x00100000, 0x01000000);
 141         /* check the first 1M in the 3rd Gig */
 142         ram_check(0x30100000, 0x31000000);
 143 #endif
 144 #if 0
 145         ram_check(0x00000000, 0x02000000);
 146 #endif
 147
 148 #if 0
 149         while(1) {
 150                 hlt();
 151         }
 152 #endif
 153 }