src/mainboard/supermicro/x6dhe_g2/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include "option_table.h"
   9 #include "pc80/mc146818rtc_early.c"
  10 #include "pc80/serial.c"
  11 #include "console/console.c"
  12 #include "lib/ramtest.c"
  13 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  14 #include "northbridge/intel/e7520/raminit.h"
  15 #include "superio/nsc/pc87427/pc87427.h"
  16 #include "cpu/x86/lapic/boot_cpu.c"
  17 #include "cpu/x86/mtrr/earlymtrr.c"
  18 #include "debug.c"
  19 #include "watchdog.c"
  20 #include "reset.c"
  21 #include "x6dhe_g2_fixups.c"
  22 #include "superio/nsc/pc87427/pc87427_early_init.c"
  23 #include "northbridge/intel/e7520/memory_initialized.c"
  24 #include "cpu/x86/bist.h"
  25
  26 #define SIO_GPIO_BASE 0x680
  27 #define SIO_XBUS_BASE 0x4880
  28
  29 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1)
  30 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, PC87427_SP2)
  31
  32 #define DEVPRES_CONFIG  ( \
  33         DEVPRES_D1F0 | \
  34         DEVPRES_D2F0 | \
  35         DEVPRES_D3F0 | \
  36         DEVPRES_D4F0 | \
  37         DEVPRES_D6F0 | \
  38         0 )
  39 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  40
  41 #define RECVENA_CONFIG  0x0708090a
  42 #define RECVENB_CONFIG  0x0708090a
  43
  44 static inline int spd_read_byte(unsigned device, unsigned address)
  45 {
  46         return smbus_read_byte(device, address);
  47 }
  48
  49 #include "northbridge/intel/e7520/raminit.c"
  50 #include "lib/generic_sdram.c"
  51 #include "arch/i386/lib/stages.c"
  52
  53 static void main(unsigned long bist)
  54 {
  55         /*
  56          *
  57          *
  58          */
  59         static const struct mem_controller mch[] = {
  60                 {
  61                         .node_id = 0,
  62                         /*
  63                         .f0 = PCI_DEV(0, 0x00, 0),
  64                         .f1 = PCI_DEV(0, 0x00, 1),
  65                         .f2 = PCI_DEV(0, 0x00, 2),
  66                         .f3 = PCI_DEV(0, 0x00, 3),
  67                         */
  68                         .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
  69                         .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
  70
  71                 }
  72         };
  73
  74         if (bist == 0) {
  75                 /* Skip this if there was a built in self test failure */
  76                 early_mtrr_init();
  77                 if (memory_initialized()) {
  78                         skip_romstage();
  79                 }
  80         }
  81         /* Setup the console */
  82         outb(0x87,0x2e);
  83         outb(0x87,0x2e);
  84         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
  85         pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  86         uart_init();
  87         console_init();
  88
  89         /* Halt if there was a built in self test failure */
  90 //      report_bist_failure(bist);
  91
  92         /* MOVE ME TO A BETTER LOCATION !!! */
  93         /* config LPC decode for flash memory access */
  94         device_t dev;
  95         dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
  96         if (dev == PCI_DEV_INVALID) {
  97                 die("Missing ich5r?");
  98         }
  99         pci_write_config32(dev, 0xe8, 0x00000000);
 100         pci_write_config8(dev, 0xf0, 0x00);
 101
 102 #if 0
 103         display_cpuid_update_microcode();
 104 #endif
 105 #if 0
 106         print_pci_devices();
 107 #endif
 108 #if 1
 109         enable_smbus();
 110 #endif
 111 #if 0
 112 //      dump_spd_registers(&cpu[0]);
 113         int i;
 114         for(i = 0; i < 1; i++) {
 115                 dump_spd_registers();
 116         }
 117 #endif
 118         disable_watchdogs();
 119 //      dump_ipmi_registers();
 120 //      mainboard_set_e7520_leds();
 121         sdram_initialize(ARRAY_SIZE(mch), mch);
 122 #if 0
 123         dump_pci_devices();
 124 #endif
 125 #if 1
 126         dump_pci_device(PCI_DEV(0, 0x00, 0));
 127         //dump_bar14(PCI_DEV(0, 0x00, 0));
 128 #endif
 129
 130 #if 0 // temporarily disabled
 131         /* Check the first 1M */
 132 //      ram_check(0x00000000, 0x000100000);
 133 //      ram_check(0x00000000, 0x000a0000);
 134         ram_check(0x00100000, 0x01000000);
 135         /* check the first 1M in the 3rd Gig */
 136         ram_check(0x30100000, 0x31000000);
 137 #endif
 138 #if 0
 139         ram_check(0x00000000, 0x02000000);
 140 #endif
 141
 142 #if 0
 143         while(1) {
 144                 hlt();
 145         }
 146 #endif
 147 }
 148