src/mainboard/supermicro/x6dhe_g2/mptable.c

   1 #include <console/console.h>
   2 #include <arch/smp/mpspec.h>
   3 #include <arch/ioapic.h>
   4 #include <device/pci.h>
   5 #include <string.h>
   6 #include <stdint.h>
   7
   8 static void *smp_write_config_table(void *v)
   9 {
  10         struct mp_config_table *mc;
  11         int bus_isa;
  12         unsigned char bus_pxhd_1;
  13         unsigned char bus_pxhd_2;
  14         unsigned char bus_esb6300_1;
  15         unsigned char bus_esb6300_2;
  16
  17         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  18
  19         mptable_init(mc, LAPIC_ADDR);
  20
  21         smp_write_processors(mc);
  22
  23         {
  24                 device_t dev;
  25
  26                 /* esb6300_2 */
  27                 dev = dev_find_slot(0, PCI_DEVFN(0x1c,0));
  28                 if (dev) {
  29                         bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  30                 } else {
  31                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n");
  32                         bus_esb6300_1 = 6;
  33                 }
  34                 /* esb6300_1 */
  35                 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
  36                 if (dev) {
  37                         bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  38                 } else {
  39                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
  40                         bus_esb6300_2 = 7;
  41                 }
  42                 /* pxhd-1 */
  43                 dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
  44                 if (dev) {
  45                         bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  46                 } else {
  47                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
  48                         bus_pxhd_1 = 2;
  49                 }
  50                 /* pxhd-2 */
  51                 dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
  52                 if (dev) {
  53                         bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  54                 } else {
  55                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
  56                         bus_pxhd_2 = 3;
  57                 }
  58         }
  59
  60         mptable_write_buses(mc, NULL, &bus_isa);
  61
  62         /* IOAPIC handling */
  63
  64         smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
  65         smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000);
  66         {
  67                 struct resource *res;
  68                 device_t dev;
  69                 /* PXHd apic 4 */
  70                 dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
  71                 if (dev) {
  72                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  73                         if (res) {
  74                                 smp_write_ioapic(mc, 0x04, 0x20, res->base);
  75                         }
  76                 } else {
  77                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
  78                         printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
  79                 }
  80                 /* PXHd apic 5 */
  81                 dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
  82                 if (dev) {
  83                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  84                         if (res) {
  85                                 smp_write_ioapic(mc, 0x05, 0x20, res->base);
  86                         }
  87                 } else {
  88                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
  89                         printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
  90                 }
  91         }
  92
  93         mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
  94
  95         /* ISA backward compatibility interrupts  */
  96         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
  97                 0x00, 0x74, 0x02, 0x10);
  98         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
  99                 0x00, 0x77, 0x02, 0x17);
 100         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 101                 0x00, 0x75, 0x02, 0x13);
 102         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 103                 0x00, 0x7c, 0x02, 0x12);
 104         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 105                 0x00, 0x7d, 0x02, 0x11);
 106         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 107                 0x03, 0x08, 0x05, 0x00);
 108         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 109                 0x03, 0x08, 0x05, 0x04);
 110         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 111                 bus_esb6300_1, 0x04, 0x03, 0x00);
 112         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 113                 bus_esb6300_1, 0x08, 0x03, 0x01);
 114         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 115                 bus_esb6300_2, 0x04, 0x02, 0x10);
 116         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 117                 bus_esb6300_2, 0x08, 0x02, 0x14);
 118
 119         /* Standard local interrupt assignments */
 120         mptable_lintsrc(mc, bus_isa);
 121
 122         /* FIXME verify I have the irqs handled for all of the risers */
 123
 124         /* Compute the checksums */
 125         return mptable_finalize(mc);
 126 }
 127
 128 unsigned long write_smp_table(unsigned long addr)
 129 {
 130         void *v;
 131         v = smp_write_floating_table(addr, 0);
 132         return (unsigned long)smp_write_config_table(v);
 133 }
 134