src/mainboard/supermicro/x6dhe_g/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "lib/ramtest.c"
  10 #include "pc80/udelay_io.c"
  11 #include "lib/delay.c"
  12 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
  13 #include "northbridge/intel/e7520/raminit.h"
  14 #include "superio/winbond/w83627hf/w83627hf.h"
  15 #include "cpu/x86/lapic/boot_cpu.c"
  16 #include "cpu/x86/mtrr/earlymtrr.c"
  17 #include "debug.c"
  18 #include "watchdog.c"
  19 #include "reset.c"
  20 #include "x6dhe_g_fixups.c"
  21 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  22 #include "northbridge/intel/e7520/memory_initialized.c"
  23 #include "cpu/x86/bist.h"
  24
  25 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  26 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
  27
  28 #define DEVPRES_CONFIG  ( \
  29         DEVPRES_D1F0 | \
  30         DEVPRES_D2F0 | \
  31         DEVPRES_D3F0 | \
  32         DEVPRES_D4F0 | \
  33         DEVPRES_D6F0 | \
  34         0 )
  35 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  36
  37 static inline int spd_read_byte(unsigned device, unsigned address)
  38 {
  39         return smbus_read_byte(device, address);
  40 }
  41
  42 #include "northbridge/intel/e7520/raminit.c"
  43 #include "lib/generic_sdram.c"
  44 #include "arch/i386/lib/stages.c"
  45
  46 static void main(unsigned long bist)
  47 {
  48         /*
  49          *
  50          *
  51          */
  52         static const struct mem_controller mch[] = {
  53                 {
  54                         .node_id = 0,
  55                         /*
  56                         .f0 = PCI_DEV(0, 0x00, 0),
  57                         .f1 = PCI_DEV(0, 0x00, 1),
  58                         .f2 = PCI_DEV(0, 0x00, 2),
  59                         .f3 = PCI_DEV(0, 0x00, 3),
  60                         */
  61                         .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
  62                         .channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
  63                 }
  64         };
  65
  66         if (bist == 0) {
  67                 /* Skip this if there was a built in self test failure */
  68                 early_mtrr_init();
  69                 if (memory_initialized()) {
  70                         skip_romstage();
  71                 }
  72         }
  73         /* Setup the console */
  74         outb(0x87,0x2e);
  75         outb(0x87,0x2e);
  76         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
  77         w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  78         uart_init();
  79         console_init();
  80
  81         /* Halt if there was a built in self test failure */
  82 //      report_bist_failure(bist);
  83
  84         /* MOVE ME TO A BETTER LOCATION !!! */
  85         /* config LPC decode for flash memory access */
  86         device_t dev;
  87         dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
  88         if (dev == PCI_DEV_INVALID) {
  89                 die("Missing esb6300?");
  90         }
  91         pci_write_config32(dev, 0xe8, 0x00000000);
  92         pci_write_config8(dev, 0xf0, 0x00);
  93
  94 #if 0
  95         display_cpuid_update_microcode();
  96 #endif
  97 #if 0
  98         print_pci_devices();
  99 #endif
 100 #if 1
 101         enable_smbus();
 102 #endif
 103 #if 0
 104 //      dump_spd_registers(&cpu[0]);
 105         int i;
 106         for(i = 0; i < 1; i++) {
 107                 dump_spd_registers();
 108         }
 109 #endif
 110         disable_watchdogs();
 111 //      dump_ipmi_registers();
 112 //      mainboard_set_e7520_leds();
 113         sdram_initialize(ARRAY_SIZE(mch), mch);
 114 #if 0
 115         dump_pci_devices();
 116 #endif
 117 #if 0
 118         dump_pci_device(PCI_DEV(0, 0x00, 0));
 119         dump_bar14(PCI_DEV(0, 0x00, 0));
 120 #endif
 121
 122 #if 0 // temporarily disabled
 123         /* Check the first 1M */
 124 //      ram_check(0x00000000, 0x000100000);
 125 //      ram_check(0x00000000, 0x000a0000);
 126         ram_check(0x00100000, 0x01000000);
 127         /* check the first 1M in the 3rd Gig */
 128         ram_check(0x30100000, 0x31000000);
 129 #endif
 130 #if 0
 131         ram_check(0x00000000, 0x02000000);
 132 #endif
 133
 134 #if 0
 135         while(1) {
 136                 hlt();
 137         }
 138 #endif
 139 }
 140