src/mainboard/supermicro/x6dhe_g/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include "option_table.h"
   9 #include "pc80/mc146818rtc_early.c"
  10 #include "pc80/serial.c"
  11 #include "console/console.c"
  12 #include "lib/ramtest.c"
  13 #include "pc80/udelay_io.c"
  14 #include "lib/delay.c"
  15 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
  16 #include "northbridge/intel/e7520/raminit.h"
  17 #include "superio/winbond/w83627hf/w83627hf.h"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "cpu/x86/mtrr/earlymtrr.c"
  20 #include "debug.c"
  21 #include "watchdog.c"
  22 #include "reset.c"
  23 #include "x6dhe_g_fixups.c"
  24 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  25 #include "northbridge/intel/e7520/memory_initialized.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #define SIO_GPIO_BASE 0x680
  29 #define SIO_XBUS_BASE 0x4880
  30
  31 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  32 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
  33
  34 #define DEVPRES_CONFIG  ( \
  35         DEVPRES_D1F0 | \
  36         DEVPRES_D2F0 | \
  37         DEVPRES_D3F0 | \
  38         DEVPRES_D4F0 | \
  39         DEVPRES_D6F0 | \
  40         0 )
  41 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  42
  43 #define RECVENA_CONFIG  0x0808090a
  44 #define RECVENB_CONFIG  0x0808090a
  45
  46 static inline int spd_read_byte(unsigned device, unsigned address)
  47 {
  48         return smbus_read_byte(device, address);
  49 }
  50
  51 #include "northbridge/intel/e7520/raminit.c"
  52 #include "lib/generic_sdram.c"
  53 #include "arch/i386/lib/stages.c"
  54
  55 static void main(unsigned long bist)
  56 {
  57         /*
  58          *
  59          *
  60          */
  61         static const struct mem_controller mch[] = {
  62                 {
  63                         .node_id = 0,
  64                         /*
  65                         .f0 = PCI_DEV(0, 0x00, 0),
  66                         .f1 = PCI_DEV(0, 0x00, 1),
  67                         .f2 = PCI_DEV(0, 0x00, 2),
  68                         .f3 = PCI_DEV(0, 0x00, 3),
  69                         */
  70                         .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
  71                         .channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
  72                 }
  73         };
  74
  75         if (bist == 0) {
  76                 /* Skip this if there was a built in self test failure */
  77                 early_mtrr_init();
  78                 if (memory_initialized()) {
  79                         skip_romstage();
  80                 }
  81         }
  82         /* Setup the console */
  83         outb(0x87,0x2e);
  84         outb(0x87,0x2e);
  85         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
  86         w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  87         uart_init();
  88         console_init();
  89
  90         /* Halt if there was a built in self test failure */
  91 //      report_bist_failure(bist);
  92
  93         /* MOVE ME TO A BETTER LOCATION !!! */
  94         /* config LPC decode for flash memory access */
  95         device_t dev;
  96         dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
  97         if (dev == PCI_DEV_INVALID) {
  98                 die("Missing esb6300?");
  99         }
 100         pci_write_config32(dev, 0xe8, 0x00000000);
 101         pci_write_config8(dev, 0xf0, 0x00);
 102
 103 #if 0
 104         display_cpuid_update_microcode();
 105 #endif
 106 #if 0
 107         print_pci_devices();
 108 #endif
 109 #if 1
 110         enable_smbus();
 111 #endif
 112 #if 0
 113 //      dump_spd_registers(&cpu[0]);
 114         int i;
 115         for(i = 0; i < 1; i++) {
 116                 dump_spd_registers();
 117         }
 118 #endif
 119         disable_watchdogs();
 120 //      dump_ipmi_registers();
 121 //      mainboard_set_e7520_leds();
 122         sdram_initialize(ARRAY_SIZE(mch), mch);
 123 #if 0
 124         dump_pci_devices();
 125 #endif
 126 #if 0
 127         dump_pci_device(PCI_DEV(0, 0x00, 0));
 128         dump_bar14(PCI_DEV(0, 0x00, 0));
 129 #endif
 130
 131 #if 0 // temporarily disabled
 132         /* Check the first 1M */
 133 //      ram_check(0x00000000, 0x000100000);
 134 //      ram_check(0x00000000, 0x000a0000);
 135         ram_check(0x00100000, 0x01000000);
 136         /* check the first 1M in the 3rd Gig */
 137         ram_check(0x30100000, 0x31000000);
 138 #endif
 139 #if 0
 140         ram_check(0x00000000, 0x02000000);
 141 #endif
 142
 143 #if 0
 144         while(1) {
 145                 hlt();
 146         }
 147 #endif
 148 }
 149