1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
7 static void *smp_write_config_table(void *v)
9 static const char sig[4] = "PCMP";
10 static const char oem[8] = "COREBOOT";
11 static const char productid[12] = "X6DHE ";
12 struct mp_config_table *mc;
13 unsigned char bus_num;
14 unsigned char bus_isa;
15 unsigned char bus_pxhd_1;
16 unsigned char bus_pxhd_2;
17 unsigned char bus_esb6300_1;
18 unsigned char bus_esb6300_2;
20 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
21 memset(mc, 0, sizeof(*mc));
23 memcpy(mc->mpc_signature, sig, sizeof(sig));
24 mc->mpc_length = sizeof(*mc); /* initially just the header */
26 mc->mpc_checksum = 0; /* not yet computed */
27 memcpy(mc->mpc_oem, oem, sizeof(oem));
28 memcpy(mc->mpc_productid, productid, sizeof(productid));
31 mc->mpc_entry_count = 0; /* No entries yet... */
32 mc->mpc_lapic = LAPIC_ADDR;
37 smp_write_processors(mc);
43 dev = dev_find_slot(0, PCI_DEVFN(0x1c,0));
45 bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
47 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n");
51 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
53 bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
54 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
57 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
62 dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
64 bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
66 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
70 dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
72 bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
74 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
79 /* define bus and isa numbers */
80 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
81 smp_write_bus(mc, bus_num, "PCI ");
83 smp_write_bus(mc, bus_isa, "ISA ");
87 smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
88 smp_write_ioapic(mc, 3, 0x20, 0xfec10000);
93 dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
95 res = find_resource(dev, PCI_BASE_ADDRESS_0);
97 smp_write_ioapic(mc, 0x04, 0x20, res->base);
100 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
101 printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
104 dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
106 res = find_resource(dev, PCI_BASE_ADDRESS_0);
108 smp_write_ioapic(mc, 0x05, 0x20, res->base);
111 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
112 printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
116 /* ISA backward compatibility interrupts */
117 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
118 bus_isa, 0x00, 0x02, 0x00);
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
120 bus_isa, 0x01, 0x02, 0x01);
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
122 bus_isa, 0x00, 0x02, 0x02);
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
124 bus_isa, 0x03, 0x02, 0x03);
125 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
126 bus_isa, 0x04, 0x02, 0x04);
127 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
128 0x00, 0x74, 0x02, 0x10);
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
130 bus_isa, 0x06, 0x02, 0x06);
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, // added
132 bus_isa, 0x07, 0x02, 0x07);
133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
134 bus_isa, 0x08, 0x02, 0x08);
135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
136 bus_isa, 0x09, 0x02, 0x09);
137 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
138 0x00, 0x77, 0x02, 0x17);
139 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
140 0x00, 0x75, 0x02, 0x13);
141 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
142 bus_isa, 0x0c, 0x02, 0x0c);
143 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
144 bus_isa, 0x0d, 0x02, 0x0d);
145 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
146 bus_isa, 0x0e, 0x02, 0x0e);
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
148 bus_isa, 0x0f, 0x02, 0x0f);
149 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
150 0x00, 0x7c, 0x02, 0x12);
151 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
152 0x00, 0x7d, 0x02, 0x11);
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
154 0x03, 0x08, 0x05, 0x00);
155 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
156 0x03, 0x08, 0x05, 0x04);
157 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
158 bus_esb6300_1, 0x04, 0x03, 0x00);
159 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
160 bus_esb6300_1, 0x08, 0x03, 0x01);
161 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
162 bus_esb6300_2, 0x04, 0x02, 0x10);
163 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
164 bus_esb6300_2, 0x08, 0x02, 0x14);
166 /* Standard local interrupt assignments */
167 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
168 bus_isa, 0x00, MP_APIC_ALL, 0x00);
169 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
170 bus_isa, 0x00, MP_APIC_ALL, 0x01);
172 /* FIXME verify I have the irqs handled for all of the risers */
174 /* Compute the checksums */
175 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
177 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
178 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
179 mc, smp_next_mpe_entry(mc));
180 return smp_next_mpe_entry(mc);
183 unsigned long write_smp_table(unsigned long addr)
186 v = smp_write_floating_table(addr);
187 return (unsigned long)smp_write_config_table(v);