src/mainboard/supermicro/x6dhe_g/mptable.c

   1 #include <console/console.h>
   2 #include <arch/smp/mpspec.h>
   3 #include <arch/ioapic.h>
   4 #include <device/pci.h>
   5 #include <string.h>
   6 #include <stdint.h>
   7
   8 static void *smp_write_config_table(void *v)
   9 {
  10         struct mp_config_table *mc;
  11         unsigned char bus_num;
  12         unsigned char bus_isa;
  13         unsigned char bus_pxhd_1;
  14         unsigned char bus_pxhd_2;
  15         unsigned char bus_esb6300_1;
  16         unsigned char bus_esb6300_2;
  17
  18         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  19
  20         mptable_init(mc, "X6DHE-G     ", LAPIC_ADDR);
  21
  22         smp_write_processors(mc);
  23
  24         {
  25                 device_t dev;
  26
  27                 /* esb6300_2 */
  28                 dev = dev_find_slot(0, PCI_DEVFN(0x1c,0));
  29                 if (dev) {
  30                         bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  31                 } else {
  32                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n");
  33                         bus_esb6300_1 = 6;
  34                 }
  35                 /* esb6300_1 */
  36                 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
  37                 if (dev) {
  38                         bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  39                         bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
  40                         bus_isa++;
  41                 } else {
  42                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
  43                         bus_esb6300_2 = 7;
  44                         bus_isa = 8;
  45                 }
  46                 /* pxhd-1 */
  47                 dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
  48                 if (dev) {
  49                         bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  50                 } else {
  51                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
  52                         bus_pxhd_1 = 2;
  53                 }
  54                 /* pxhd-2 */
  55                 dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
  56                 if (dev) {
  57                         bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  58                 } else {
  59                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
  60                         bus_pxhd_2 = 3;
  61                 }
  62         }
  63
  64         /* define bus and isa numbers */
  65         for(bus_num = 0; bus_num < bus_isa; bus_num++) {
  66                 smp_write_bus(mc, bus_num, "PCI   ");
  67         }
  68         smp_write_bus(mc, bus_isa, "ISA   ");
  69
  70         /* IOAPIC handling */
  71
  72         smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
  73         smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000);
  74         {
  75                 struct resource *res;
  76                 device_t dev;
  77                 /* PXHd apic 4 */
  78                 dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
  79                 if (dev) {
  80                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  81                         if (res) {
  82                                 smp_write_ioapic(mc, 0x04, 0x20, res->base);
  83                         }
  84                 } else {
  85                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
  86                         printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
  87                 }
  88                 /* PXHd apic 5 */
  89                 dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
  90                 if (dev) {
  91                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  92                         if (res) {
  93                                 smp_write_ioapic(mc, 0x05, 0x20, res->base);
  94                         }
  95                 } else {
  96                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
  97                         printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
  98                 }
  99         }
 100
 101         mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
 102
 103         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 104                 0x00, 0x74, 0x02, 0x10);
 105         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 106                 0x00, 0x77, 0x02, 0x17);
 107         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 108                 0x00, 0x75, 0x02, 0x13);
 109         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 110                 0x00, 0x7c, 0x02, 0x12);
 111         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 112                 0x00, 0x7d, 0x02, 0x11);
 113         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 114                 0x03, 0x08, 0x05, 0x00);
 115         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 116                 0x03, 0x08, 0x05, 0x04);
 117         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 118                 bus_esb6300_1, 0x04, 0x03, 0x00);
 119         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 120                 bus_esb6300_1, 0x08, 0x03, 0x01);
 121         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 122                 bus_esb6300_2, 0x04, 0x02, 0x10);
 123         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 124                 bus_esb6300_2, 0x08, 0x02, 0x14);
 125
 126         /* Standard local interrupt assignments */
 127         smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 128                 bus_isa, 0x00, MP_APIC_ALL, 0x00);
 129         smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 130                 bus_isa, 0x00, MP_APIC_ALL, 0x01);
 131
 132         /* FIXME verify I have the irqs handled for all of the risers */
 133
 134         /* Compute the checksums */
 135         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 136
 137         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 138         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 139                 mc, smp_next_mpe_entry(mc));
 140         return smp_next_mpe_entry(mc);
 141 }
 142
 143 unsigned long write_smp_table(unsigned long addr)
 144 {
 145         void *v;
 146         v = smp_write_floating_table(addr);
 147         return (unsigned long)smp_write_config_table(v);
 148 }
 149