src/mainboard/supermicro/x6dai_g/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <stdlib.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "lib/ramtest.c"
  15 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
  16 #include "northbridge/intel/e7525/raminit.h"
  17 #include "superio/winbond/w83627hf/w83627hf.h"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "cpu/x86/mtrr/earlymtrr.c"
  20 #include "debug.c"
  21 #include "watchdog.c"
  22 #include "reset.c"
  23 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  24 #include "northbridge/intel/e7525/memory_initialized.c"
  25 #include "cpu/x86/bist.h"
  26
  27
  28 #define SIO_GPIO_BASE 0x680
  29 #define SIO_XBUS_BASE 0x4880
  30
  31 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  32 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
  33
  34 #define DEVPRES_CONFIG  ( \
  35         DEVPRES_D1F0 | \
  36         DEVPRES_D2F0 | \
  37         DEVPRES_D3F0 | \
  38         DEVPRES_D4F0 | \
  39         DEVPRES_D6F0 | \
  40         0 )
  41 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  42
  43 #define RECVENA_CONFIG  0x0808090a
  44 #define RECVENB_CONFIG  0x0808090a
  45
  46 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  47 {
  48         /* nothing to do */
  49 }
  50 static inline int spd_read_byte(unsigned device, unsigned address)
  51 {
  52         return smbus_read_byte(device, address);
  53 }
  54
  55 #include "northbridge/intel/e7525/raminit.c"
  56 #include "lib/generic_sdram.c"
  57
  58
  59 static void main(unsigned long bist)
  60 {
  61         /*
  62          *
  63          *
  64          */
  65         static const struct mem_controller mch[] = {
  66                 {
  67                         .node_id = 0,
  68                         .f0 = PCI_DEV(0, 0x00, 0),
  69                         .f1 = PCI_DEV(0, 0x00, 1),
  70                         .f2 = PCI_DEV(0, 0x00, 2),
  71                         .f3 = PCI_DEV(0, 0x00, 3),
  72                         .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
  73                         .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
  74                 }
  75         };
  76
  77         if (bist == 0) {
  78                 /* Skip this if there was a built in self test failure */
  79                 early_mtrr_init();
  80                 if (memory_initialized()) {
  81                         asm volatile ("jmp __cpu_reset");
  82                 }
  83         }
  84         /* Setup the console */
  85         outb(0x87,0x2e);
  86         outb(0x87,0x2e);
  87         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
  88         w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  89         uart_init();
  90         console_init();
  91
  92         /* MOVE ME TO A BETTER LOCATION !!! */
  93         /* config LPC decode for flash memory access */
  94         device_t dev;
  95         dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
  96         if (dev == PCI_DEV_INVALID) {
  97                 die("Missing 6300ESB?");
  98         }
  99         pci_write_config32(dev, 0xe8, 0x00000000);
 100         pci_write_config8(dev, 0xf0, 0x00);
 101
 102 #if 0
 103         display_cpuid_update_microcode();
 104 #endif
 105 #if 0
 106         print_pci_devices();
 107 #endif
 108 #if 1
 109         enable_smbus();
 110 #endif
 111 #if 0
 112         int i;
 113         for(i = 0; i < 1; i++) {
 114                 dump_spd_registers();
 115         }
 116 #endif
 117         disable_watchdogs();
 118         sdram_initialize(ARRAY_SIZE(mch), mch);
 119 #if 1
 120         dump_pci_device(PCI_DEV(0, 0x00, 0));
 121 //      dump_bar14(PCI_DEV(0, 0x00, 0));
 122 #endif
 123
 124 #if 0 // temporarily disabled
 125         /* Check the first 1M */
 126 //      ram_check(0x00000000, 0x000100000);
 127 //      ram_check(0x00000000, 0x000a0000);
 128         ram_check(0x00100000, 0x01000000);
 129         /* check the first 1M in the 3rd Gig */
 130         ram_check(0x30100000, 0x31000000);
 131 #endif
 132 #if 0
 133         ram_check(0x00000000, 0x02000000);
 134 #endif
 135
 136 #if 0
 137         while(1) {
 138                 hlt();
 139         }
 140 #endif
 141 }