src/mainboard/supermicro/x6dai_g/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "lib/ramtest.c"
  10 #include "pc80/udelay_io.c"
  11 #include "lib/delay.c"
  12 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
  13 #include "northbridge/intel/e7525/raminit.h"
  14 #include "superio/winbond/w83627hf/w83627hf.h"
  15 #include "cpu/x86/lapic/boot_cpu.c"
  16 #include "cpu/x86/mtrr/earlymtrr.c"
  17 #include "debug.c"
  18 #include "watchdog.c"
  19 #include "reset.c"
  20 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  21 #include "northbridge/intel/e7525/memory_initialized.c"
  22 #include "cpu/x86/bist.h"
  23
  24 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  25 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
  26
  27 #define DEVPRES_CONFIG  ( \
  28         DEVPRES_D1F0 | \
  29         DEVPRES_D2F0 | \
  30         DEVPRES_D3F0 | \
  31         DEVPRES_D4F0 | \
  32         DEVPRES_D6F0 | \
  33         0 )
  34 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  35
  36 static inline int spd_read_byte(unsigned device, unsigned address)
  37 {
  38         return smbus_read_byte(device, address);
  39 }
  40
  41 #include "northbridge/intel/e7525/raminit.c"
  42 #include "lib/generic_sdram.c"
  43 #include "arch/i386/lib/stages.c"
  44
  45 static void main(unsigned long bist)
  46 {
  47         /*
  48          *
  49          *
  50          */
  51         static const struct mem_controller mch[] = {
  52                 {
  53                         .node_id = 0,
  54                         .f0 = PCI_DEV(0, 0x00, 0),
  55                         .f1 = PCI_DEV(0, 0x00, 1),
  56                         .f2 = PCI_DEV(0, 0x00, 2),
  57                         .f3 = PCI_DEV(0, 0x00, 3),
  58                         .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
  59                         .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
  60                 }
  61         };
  62
  63         if (bist == 0) {
  64                 /* Skip this if there was a built in self test failure */
  65                 early_mtrr_init();
  66                 if (memory_initialized()) {
  67                         skip_romstage();
  68                 }
  69         }
  70         /* Setup the console */
  71         outb(0x87,0x2e);
  72         outb(0x87,0x2e);
  73         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
  74         w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  75         uart_init();
  76         console_init();
  77
  78         /* MOVE ME TO A BETTER LOCATION !!! */
  79         /* config LPC decode for flash memory access */
  80         device_t dev;
  81         dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
  82         if (dev == PCI_DEV_INVALID) {
  83                 die("Missing 6300ESB?");
  84         }
  85         pci_write_config32(dev, 0xe8, 0x00000000);
  86         pci_write_config8(dev, 0xf0, 0x00);
  87
  88 #if 0
  89         display_cpuid_update_microcode();
  90 #endif
  91 #if 0
  92         print_pci_devices();
  93 #endif
  94 #if 1
  95         enable_smbus();
  96 #endif
  97 #if 0
  98         int i;
  99         for(i = 0; i < 1; i++) {
 100                 dump_spd_registers();
 101         }
 102 #endif
 103         disable_watchdogs();
 104         sdram_initialize(ARRAY_SIZE(mch), mch);
 105 #if 1
 106         dump_pci_device(PCI_DEV(0, 0x00, 0));
 107 //      dump_bar14(PCI_DEV(0, 0x00, 0));
 108 #endif
 109
 110 #if 0 // temporarily disabled
 111         /* Check the first 1M */
 112 //      ram_check(0x00000000, 0x000100000);
 113 //      ram_check(0x00000000, 0x000a0000);
 114         ram_check(0x00100000, 0x01000000);
 115         /* check the first 1M in the 3rd Gig */
 116         ram_check(0x30100000, 0x31000000);
 117 #endif
 118 #if 0
 119         ram_check(0x00000000, 0x02000000);
 120 #endif
 121
 122 #if 0
 123         while(1) {
 124                 hlt();
 125         }
 126 #endif
 127 }
 128