1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
7 static void *smp_write_config_table(void *v)
9 static const char sig[4] = "PCMP";
10 static const char oem[8] = "COREBOOT";
11 static const char productid[12] = "X6DAI-G ";
12 struct mp_config_table *mc;
13 unsigned char bus_num;
14 unsigned char bus_isa;
15 unsigned char bus_6300;
17 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
18 memset(mc, 0, sizeof(*mc));
20 memcpy(mc->mpc_signature, sig, sizeof(sig));
21 mc->mpc_length = sizeof(*mc); /* initially just the header */
23 mc->mpc_checksum = 0; /* not yet computed */
24 memcpy(mc->mpc_oem, oem, sizeof(oem));
25 memcpy(mc->mpc_productid, productid, sizeof(productid));
28 mc->mpc_entry_count = 0; /* No entries yet... */
29 mc->mpc_lapic = LAPIC_ADDR;
34 smp_write_processors(mc);
40 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
42 bus_6300 = pci_read_config8(dev, PCI_SECONDARY_BUS);
43 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
47 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
53 /* define bus and isa numbers */
54 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
55 smp_write_bus(mc, bus_num, "PCI ");
57 smp_write_bus(mc, bus_isa, "ISA ");
61 smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
62 smp_write_ioapic(mc, 3, 0x20, 0xfec10000);
64 /* ISA backward compatibility interrupts */
65 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
66 bus_isa, 0x00, 0x02, 0x00);
67 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
68 bus_isa, 0x01, 0x02, 0x01);
69 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
70 bus_isa, 0x00, 0x02, 0x02);
71 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
72 bus_isa, 0x03, 0x02, 0x03);
73 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
74 bus_isa, 0x04, 0x02, 0x04);
75 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
76 0x00, 0x74, 0x02, 0x10);
77 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
78 bus_isa, 0x06, 0x02, 0x06);
79 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
80 bus_isa, 0x07, 0x02, 0x07);
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
82 bus_isa, 0x08, 0x02, 0x08);
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
84 bus_isa, 0x09, 0x02, 0x09);
85 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
86 0x00, 0x77, 0x02, 0x17);
87 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
88 0x00, 0x75, 0x02, 0x13);
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
90 bus_isa, 0x0c, 0x02, 0x0c);
91 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
92 bus_isa, 0x0d, 0x02, 0x0d);
93 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
94 bus_isa, 0x0e, 0x02, 0x0e);
95 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
96 bus_isa, 0x0f, 0x02, 0x0f);
97 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
98 0x00, 0x7c, 0x02, 0x12);
99 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
100 0x00, 0x7d, 0x02, 0x11);
101 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
102 0x00, 0x7d, 0x02, 0x11);
103 /* Slot 1 function 0 */
104 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
105 4, 0x04, 0x03, 0x00);
106 /* Slot 2 function 0 */
107 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
108 4, 0x0c, 0x03, 0x01);
109 /* Slot 3 function 0 */
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
111 bus_6300, 0x20, 0x02, 0x14);
112 /* Slot 4 function 0 */
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
114 bus_6300, 0x08, 0x02, 0x15);
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
117 bus_6300, 0x0c, 0x02, 0x16);
119 /* Standard local interrupt assignments */
120 // smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
121 // bus_isa, 0x00, MP_APIC_ALL, 0x00);
122 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
123 bus_isa, 0x00, MP_APIC_ALL, 0x01);
125 /* There is no extension information... */
127 /* Compute the checksums */
128 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
130 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
131 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
132 mc, smp_next_mpe_entry(mc));
133 return smp_next_mpe_entry(mc);
136 unsigned long write_smp_table(unsigned long addr)
139 v = smp_write_floating_table(addr);
140 return (unsigned long)smp_write_config_table(v);