1 uses CONFIG_HAVE_MP_TABLE
3 uses CONFIG_HAVE_PIRQ_TABLE
4 uses CONFIG_USE_FALLBACK_IMAGE
5 uses CONFIG_HAVE_FALLBACK_BOOT
6 uses CONFIG_HAVE_HARD_RESET
7 uses CONFIG_IRQ_SLOT_COUNT
8 uses CONFIG_HAVE_OPTION_TABLE
9 uses CONFIG_LOGICAL_CPUS
13 uses CONFIG_FALLBACK_SIZE
15 uses CONFIG_ROM_SECTION_SIZE
16 uses CONFIG_ROM_IMAGE_SIZE
17 uses CONFIG_ROM_SECTION_SIZE
18 uses CONFIG_ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_ROM_PAYLOAD_START
21 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
22 uses CONFIG_PRECOMPRESSED_PAYLOAD
23 uses CONFIG_PAYLOAD_SIZE
25 uses CONFIG_XIP_ROM_SIZE
26 uses CONFIG_XIP_ROM_BASE
27 uses CONFIG_STACK_SIZE
29 uses CONFIG_USE_OPTION_TABLE
30 uses CONFIG_LB_CKS_RANGE_START
31 uses CONFIG_LB_CKS_RANGE_END
32 uses CONFIG_LB_CKS_LOC
34 uses CONFIG_MAINBOARD_PART_NUMBER
35 uses CONFIG_MAINBOARD_VENDOR
36 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
37 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
38 uses COREBOOT_EXTRA_VERSION
39 uses CONFIG_UDELAY_TSC
40 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
43 uses CONFIG_CONSOLE_SERIAL8250
44 uses CONFIG_TTYS0_BAUD
45 uses CONFIG_TTYS0_BASE
47 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
48 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
49 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
50 uses CONFIG_CONSOLE_BTEXT
53 uses CONFIG_CROSS_COMPILE
62 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
64 default CONFIG_ROM_SIZE=1048576
67 ## Build code for the fallback boot
69 default CONFIG_HAVE_FALLBACK_BOOT=1
72 ## Delay timer options
75 default CONFIG_UDELAY_TSC=1
76 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
79 ## Build code to reset the motherboard from coreboot
81 default CONFIG_HAVE_HARD_RESET=1
84 ## Build code to export a programmable irq routing table
86 default CONFIG_HAVE_PIRQ_TABLE=1
87 default CONFIG_IRQ_SLOT_COUNT=16
90 ## Build code to export an x86 MP table
91 ## Useful for specifying IRQ routing values
93 default CONFIG_HAVE_MP_TABLE=1
96 ## Build code to export a CMOS option table
98 default CONFIG_HAVE_OPTION_TABLE=1
101 ## Move the default coreboot cmos range off of AMD RTC registers
103 default CONFIG_LB_CKS_RANGE_START=49
104 default CONFIG_LB_CKS_RANGE_END=122
105 default CONFIG_LB_CKS_LOC=123
108 ## Build code for SMP support
109 ## Only worry about 2 micro processors
112 default CONFIG_MAX_CPUS=4
113 default CONFIG_LOGICAL_CPUS=0
116 ## Build code to setup a generic IOAPIC
118 default CONFIG_IOAPIC=1
121 ## Clean up the motherboard id strings
123 default CONFIG_MAINBOARD_PART_NUMBER="X6DAI"
124 default CONFIG_MAINBOARD_VENDOR= "Supermicro"
125 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
126 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6780
129 ### coreboot layout values
132 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
133 default CONFIG_ROM_IMAGE_SIZE = 65536
136 ## Use a small 8K stack
138 default CONFIG_STACK_SIZE=0x2000
141 ## Use a small 32K heap
143 default CONFIG_HEAP_SIZE=0x8000
147 ### Compute the location and size of where this firmware image
148 ### (coreboot plus bootloader) will live in the boot rom chip.
150 default CONFIG_FALLBACK_SIZE=131072
153 ## Coreboot C code runs at this location in RAM
155 default CONFIG_RAMBASE=0x00004000
158 ## Load the payload from the ROM
160 default CONFIG_ROM_PAYLOAD=1
164 ### Defaults of options that you may want to override in the target config file
168 ## The default compiler
170 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
174 ## Disable the gdb stub by default
176 default CONFIG_GDB_STUB=0
179 ## The Serial Console
182 # To Enable the Serial Console
183 default CONFIG_CONSOLE_SERIAL8250=1
185 ## Select the serial console baud rate
186 default CONFIG_TTYS0_BAUD=115200
187 #default CONFIG_TTYS0_BAUD=57600
188 #default CONFIG_TTYS0_BAUD=38400
189 #default CONFIG_TTYS0_BAUD=19200
190 #default CONFIG_TTYS0_BAUD=9600
191 #default CONFIG_TTYS0_BAUD=4800
192 #default CONFIG_TTYS0_BAUD=2400
193 #default CONFIG_TTYS0_BAUD=1200
195 # Select the serial console base port
196 default CONFIG_TTYS0_BASE=0x3f8
198 # Select the serial protocol
199 # This defaults to 8 data bits, 1 stop bit, and no parity
200 default CONFIG_TTYS0_LCS=0x3
203 ### Select the coreboot loglevel
205 ## EMERG 1 system is unusable
206 ## ALERT 2 action must be taken immediately
207 ## CRIT 3 critical conditions
208 ## ERR 4 error conditions
209 ## WARNING 5 warning conditions
210 ## NOTICE 6 normal but significant condition
211 ## INFO 7 informational
212 ## CONFIG_DEBUG 8 debug-level messages
213 ## SPEW 9 Way too many details
215 ## Request this level of debugging output
216 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
217 ## At a maximum only compile in this level of debugging
218 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
221 ## Select power on after power fail setting
222 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
225 ## Don't enable the btext console
227 default CONFIG_CONSOLE_BTEXT=0
236 default CONFIG_CBFS=0