1 uses CONFIG_HAVE_MP_TABLE
2 uses CONFIG_HAVE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_IRQ_SLOT_COUNT
7 uses CONFIG_HAVE_OPTION_TABLE
8 uses CONFIG_LOGICAL_CPUS
12 uses CONFIG_FALLBACK_SIZE
14 uses CONFIG_ROM_SECTION_SIZE
15 uses CONFIG_ROM_IMAGE_SIZE
16 uses CONFIG_ROM_SECTION_SIZE
17 uses CONFIG_ROM_SECTION_OFFSET
18 uses CONFIG_ROM_PAYLOAD
19 uses CONFIG_ROM_PAYLOAD_START
20 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
21 uses CONFIG_PRECOMPRESSED_PAYLOAD
22 uses CONFIG_PAYLOAD_SIZE
24 uses CONFIG_XIP_ROM_SIZE
25 uses CONFIG_XIP_ROM_BASE
26 uses CONFIG_STACK_SIZE
28 uses CONFIG_USE_OPTION_TABLE
29 uses CONFIG_LB_CKS_RANGE_START
30 uses CONFIG_LB_CKS_RANGE_END
31 uses CONFIG_LB_CKS_LOC
33 uses CONFIG_MAINBOARD_PART_NUMBER
34 uses CONFIG_MAINBOARD_VENDOR
35 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
36 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
37 uses COREBOOT_EXTRA_VERSION
38 uses CONFIG_UDELAY_TSC
39 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
42 uses CONFIG_CONSOLE_SERIAL8250
43 uses CONFIG_TTYS0_BAUD
44 uses CONFIG_TTYS0_BASE
46 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
47 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
48 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
49 uses CONFIG_CONSOLE_BTEXT
52 uses CONFIG_CROSS_COMPILE
61 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
63 default CONFIG_ROM_SIZE=1048576
66 ## Build code for the fallback boot
68 default CONFIG_HAVE_FALLBACK_BOOT=1
71 ## Delay timer options
74 default CONFIG_UDELAY_TSC=1
75 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
78 ## Build code to reset the motherboard from coreboot
80 default CONFIG_HAVE_HARD_RESET=1
83 ## Build code to export a programmable irq routing table
85 default CONFIG_HAVE_PIRQ_TABLE=1
86 default CONFIG_IRQ_SLOT_COUNT=16
89 ## Build code to export an x86 MP table
90 ## Useful for specifying IRQ routing values
92 default CONFIG_HAVE_MP_TABLE=1
95 ## Build code to export a CMOS option table
97 default CONFIG_HAVE_OPTION_TABLE=1
100 ## Move the default coreboot cmos range off of AMD RTC registers
102 default CONFIG_LB_CKS_RANGE_START=49
103 default CONFIG_LB_CKS_RANGE_END=122
104 default CONFIG_LB_CKS_LOC=123
107 ## Build code for SMP support
108 ## Only worry about 2 micro processors
111 default CONFIG_MAX_CPUS=4
112 default CONFIG_LOGICAL_CPUS=0
115 ## Build code to setup a generic IOAPIC
117 default CONFIG_IOAPIC=1
120 ## Clean up the motherboard id strings
122 default CONFIG_MAINBOARD_PART_NUMBER="X6DAI"
123 default CONFIG_MAINBOARD_VENDOR= "Supermicro"
124 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
125 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6780
128 ### coreboot layout values
131 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
132 default CONFIG_ROM_IMAGE_SIZE = 65536
135 ## Use a small 8K stack
137 default CONFIG_STACK_SIZE=0x2000
140 ## Use a small 32K heap
142 default CONFIG_HEAP_SIZE=0x8000
146 ### Compute the location and size of where this firmware image
147 ### (coreboot plus bootloader) will live in the boot rom chip.
149 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
152 ## Coreboot C code runs at this location in RAM
154 default CONFIG_RAMBASE=0x00004000
157 ## Load the payload from the ROM
159 default CONFIG_ROM_PAYLOAD=1
163 ### Defaults of options that you may want to override in the target config file
167 ## The default compiler
169 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
173 ## Disable the gdb stub by default
175 default CONFIG_GDB_STUB=0
178 ## The Serial Console
181 # To Enable the Serial Console
182 default CONFIG_CONSOLE_SERIAL8250=1
184 ## Select the serial console baud rate
185 default CONFIG_TTYS0_BAUD=115200
186 #default CONFIG_TTYS0_BAUD=57600
187 #default CONFIG_TTYS0_BAUD=38400
188 #default CONFIG_TTYS0_BAUD=19200
189 #default CONFIG_TTYS0_BAUD=9600
190 #default CONFIG_TTYS0_BAUD=4800
191 #default CONFIG_TTYS0_BAUD=2400
192 #default CONFIG_TTYS0_BAUD=1200
194 # Select the serial console base port
195 default CONFIG_TTYS0_BASE=0x3f8
197 # Select the serial protocol
198 # This defaults to 8 data bits, 1 stop bit, and no parity
199 default CONFIG_TTYS0_LCS=0x3
202 ### Select the coreboot loglevel
204 ## EMERG 1 system is unusable
205 ## ALERT 2 action must be taken immediately
206 ## CRIT 3 critical conditions
207 ## ERR 4 error conditions
208 ## WARNING 5 warning conditions
209 ## NOTICE 6 normal but significant condition
210 ## INFO 7 informational
211 ## CONFIG_DEBUG 8 debug-level messages
212 ## SPEW 9 Way too many details
214 ## Request this level of debugging output
215 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
216 ## At a maximum only compile in this level of debugging
217 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
220 ## Select power on after power fail setting
221 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
224 ## Don't enable the btext console
226 default CONFIG_CONSOLE_BTEXT=0