2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <arch/smp/mpspec.h>
23 #include <device/pci.h>
27 #include <cpu/amd/amdfam10_sysconf.h>
29 extern u8 bus_sr5650[14];
30 extern u8 bus_sp5100[2];
32 extern u32 apicid_sp5100;
34 extern u32 sbdn_sr5650;
35 extern u32 sbdn_sp5100;
38 static void *smp_write_config_table(void *v)
40 struct mp_config_table *mc;
44 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
46 mptable_init(mc, LOCAL_APIC_ADDR);
48 smp_write_processors(mc);
53 apicid_sr5650 = apicid_sp5100 + 1;
55 mptable_write_buses(mc, NULL, &bus_isa);
56 /* I/O APICs: APIC ID Version State Address */
62 dev = dev_find_slot(0, //bus_sp5100[0], TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
63 PCI_DEVFN(sbdn_sp5100 + 0x14, 0));
65 dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
66 smp_write_ioapic(mc, apicid_sp5100, 0x11, dword);
68 /* Initialize interrupt mapping */
70 byte = pci_read_config8(dev, 0x63);
72 byte |= 0; /* 0: INTA, ...., 7: INTH */
73 pci_write_config8(dev, 0x63, byte);
76 dword = pci_read_config32(dev, 0xac);
78 dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
79 /* dword |= 1<<22; PIC and APIC co exists */
80 pci_write_config32(dev, 0xac, dword);
83 * 00:12.0: PROG SATA : INT F
91 * 00:14.2: Prog HDA : INT E
96 dev = dev_find_slot(0, PCI_DEVFN(0, 0));
98 pci_write_config32(dev, 0xF8, 0x1);
99 dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
100 smp_write_ioapic(mc, apicid_sp5100+1, 0x11, dword);
104 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
105 #define IO_LOCAL_INT(type, intr, apicid, pin) \
106 smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
108 mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0);
110 /* PCI interrupts are level triggered, and are
111 * associated with a specific bus/device/function tuple.
113 #if CONFIG_GENERATE_ACPI_TABLES == 0
114 #define PCI_INT(bus, dev, fn, pin) \
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sp5100, (pin))
117 #define PCI_INT(bus, dev, fn, pin)
120 PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
121 PCI_INT(0x0, 0x12, 0x1, 0x11);
122 PCI_INT(0x0, 0x13, 0x0, 0x12);
123 PCI_INT(0x0, 0x13, 0x1, 0x13);
124 //PCI_INT(0x0, 0x14, 0x0, 0x10);
127 PCI_INT(0x0, 0x11, 0x0, 0x16);
129 /* HD Audio: b0:d20:f1:reg63 should be 0. */
130 PCI_INT(0x0, 0x14, 0x2, 0x10);
132 /* on board NIC & Slot PCIE. */
133 /* configuration B doesnt need dev 5,6,7 */
135 * PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11);
136 * PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12);
137 * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13);
139 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((2)<<2)|(0)), apicid_sp5100+1, 28); /* dev 2 */
140 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((4)<<2)|(0)), apicid_sp5100+1, 28); /* dev 4 */
141 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sp5100+1, 30); /* dev 11 */
142 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sp5100+1, 30); /* dev 12 */
144 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[2], (((0)<<2)|(0)), apicid_sp5100+1, 0); /* card behind dev2 */
145 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[4], (((0)<<2)|(0)), apicid_sp5100+1, 20);
146 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[4], (((0)<<2)|(1)), apicid_sp5100+1, 21); /* NIC */
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[11], (((0)<<2)|(0)), apicid_sp5100+1, 8);
148 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[11], (((0)<<2)|(1)), apicid_sp5100+1, 9); /* card behind dev11 */
149 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[12], (((0)<<2)|(0)), apicid_sp5100+1, 12);
150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[12], (((0)<<2)|(1)), apicid_sp5100+1, 13); /* card behind dev12 */
154 PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
155 PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
156 PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
157 PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
160 PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
161 PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
162 PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
163 PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
166 PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
167 PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
168 PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
169 PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
171 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
172 IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
173 IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
174 /* There is no extension information... */
176 /* Compute the checksums */
177 return mptable_finalize(mc);
180 unsigned long write_smp_table(unsigned long addr)
183 v = smp_write_floating_table(addr, 0);
184 return (unsigned long)smp_write_config_table(v);