2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
24 #include <boot/tables.h>
25 #include <cpu/x86/msr.h>
26 #include <cpu/amd/mtrr.h>
27 #include <device/pci_def.h>
28 #include <southbridge/amd/sb700/sb700.h>
29 #include <southbridge/amd/sr5650/cmn.h>
32 #define SMBUS_IO_BASE 0x6000
34 uint64_t uma_memory_base, uma_memory_size;
36 void set_pcie_reset(void);
37 void set_pcie_dereset(void);
38 u8 is_dev3_present(void);
40 /* 780 board use this function*/
41 u8 is_dev3_present(void)
47 * TODO: Add the routine info of each PCIE_RESET_L.
48 * TODO: Add the reset of each PCIE_RESET_L.
49 * PCIE_RESET_GPIO1 -> Slot 0
50 * PCIE_RESET_GPIO2 -> On-board NIC Bcm5709
51 * PCIE_RESET_GPIO3 -> TMS
52 * PCIE_RESET_GPIO4 -> Slot 1
53 * PCIE_RESET_GPIO5 -> Slot 2
55 void set_pcie_reset(void)
57 device_t pcie_core_dev;
59 pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
60 set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828);
61 set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028);
64 void set_pcie_dereset(void)
66 device_t pcie_core_dev;
68 pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
69 set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F);
70 set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F);
73 /*************************************************
74 * enable the dedicated function in h8scm board.
75 * This function called early than sr5650_enable.
76 *************************************************/
77 static void h8scm_enable(device_t dev)
79 /* Leave it for furture use. */
80 /* struct mainboard_config *mainboard =
81 (struct mainboard_config *)dev->chip_info; */
83 printk(BIOS_INFO, "Mainboard H8SCM Enable. dev=0x%p\n", dev);
87 /* TOP_MEM: the top of DRAM below 4G */
90 (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
91 __func__, msr.lo, msr.hi);
93 /* TOP_MEM2: the top of DRAM above 4G */
94 msr2 = rdmsr(TOP_MEM2);
96 (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
97 __func__, msr2.lo, msr2.hi);
98 #if (CONFIG_GFXUMA == 1)
100 /* refer to UMA Size Consideration in 780 BDG. */
102 case 0x10000000: /* 256M system memory */
103 uma_memory_size = 0x4000000; /* 64M recommended UMA */
106 case 0x20000000: /* 512M system memory */
107 uma_memory_size = 0x8000000; /* 128M recommended UMA */
110 default: /* 1GB and above system memory */
111 uma_memory_size = 0x10000000; /* 256M recommended UMA */
116 uma_memory_size = 0;//0x8000000; /* 128M recommended UMA */
118 uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
119 printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
120 __func__, uma_memory_size, uma_memory_base);
123 /* get_ide_dma66(); */
126 int add_mainboard_resources(struct lb_memory *mem)
128 /* UMA is removed from system memory in the northbridge code, but
129 * in some circumstances we want the memory mentioned as reserved.
131 #if (CONFIG_GFXUMA == 1)
132 printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
133 uma_memory_base, uma_memory_size);
134 lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
140 struct chip_operations mainboard_ops = {
141 CHIP_NAME("AMD H8SCM Mainboard")
142 .enable_dev = h8scm_enable,