src/mainboard/supermicro/h8qme_fam10/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #define FAM10_SCAN_PCI_BUS 0
  23 #define FAM10_ALLOCATE_IO_RANGE 1
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include <device/pci_def.h>
  28 #include <device/pci_ids.h>
  29 #include <arch/io.h>
  30 #include <device/pnp_def.h>
  31 #include <arch/romcc_io.h>
  32 #include <cpu/x86/lapic.h>
  33
  34 #include <console/console.h>
  35 #include <lib.h>
  36
  37 #include <cpu/amd/model_10xxx_rev.h>
  38
  39 // for enable the FAN
  40 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  41 #include "northbridge/amd/amdfam10/raminit.h"
  42 #include "northbridge/amd/amdfam10/amdfam10.h"
  43 #include "cpu/amd/model_10xxx/apic_timer.c"
  44 #include "lib/delay.c"
  45 #include "cpu/x86/lapic/boot_cpu.c"
  46 #include "northbridge/amd/amdfam10/reset_test.c"
  47 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  48 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  49
  50 #include "cpu/x86/bist.h"
  51
  52 #include "northbridge/amd/amdfam10/debug.c"
  53
  54 #include "cpu/x86/mtrr/earlymtrr.c"
  55
  56 #include "northbridge/amd/amdfam10/setup_resource_map.c"
  57
  58 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  59
  60 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  61
  62 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  63 {
  64 #define SMBUS_SWITCH1 0x70
  65 #define SMBUS_SWITCH2 0x72
  66         smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f);
  67         smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f);
  68 }
  69
  70 static inline int spd_read_byte(unsigned device, unsigned address)
  71 {
  72         return smbus_read_byte(device, address);
  73 }
  74
  75 #include "northbridge/amd/amdfam10/amdfam10.h"
  76
  77 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
  78 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
  79
  80 #include "resourcemap.c"
  81
  82 #include "cpu/amd/quadcore/quadcore.c"
  83
  84 #define MCP55_PCI_E_X_0 4
  85
  86 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
  87 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
  88
  89
  90
  91 #include "cpu/amd/car/post_cache_as_ram.c"
  92
  93 #include "cpu/amd/microcode/microcode.c"
  94 #include "cpu/amd/model_10xxx/update_microcode.c"
  95 #include "cpu/amd/model_10xxx/init_cpus.c"
  96
  97
  98 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
  99 #include "northbridge/amd/amdfam10/early_ht.c"
 100
 101 static void sio_setup(void)
 102 {
 103         uint32_t dword;
 104         uint8_t byte;
 105         enable_smbus();
 106 //      smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
 107         smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
 108
 109         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 110         byte |= 0x20;
 111         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 112
 113         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 114         dword |= (1<<0);
 115         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 116
 117         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
 118         dword |= (1<<16);
 119         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 120
 121 }
 122
 123 #include "spd_addr.h"
 124
 125 #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
 126 #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
 127 #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
 128 static void write_GPIO(void)
 129 {
 130         pnp_enter_ext_func_mode(GPIO1_DEV);
 131         pnp_set_logical_device(GPIO1_DEV);
 132         pnp_write_config(GPIO1_DEV, 0x30, 0x01);
 133         pnp_write_config(GPIO1_DEV, 0x60, 0x00);
 134         pnp_write_config(GPIO1_DEV, 0x61, 0x00);
 135         pnp_write_config(GPIO1_DEV, 0x62, 0x00);
 136         pnp_write_config(GPIO1_DEV, 0x63, 0x00);
 137         pnp_write_config(GPIO1_DEV, 0x70, 0x00);
 138         pnp_write_config(GPIO1_DEV, 0xf0, 0xff);
 139         pnp_write_config(GPIO1_DEV, 0xf1, 0xff);
 140         pnp_write_config(GPIO1_DEV, 0xf2, 0x00);
 141         pnp_exit_ext_func_mode(GPIO1_DEV);
 142
 143         pnp_enter_ext_func_mode(GPIO2_DEV);
 144         pnp_set_logical_device(GPIO2_DEV);
 145         pnp_write_config(GPIO2_DEV, 0x30, 0x01);
 146         pnp_write_config(GPIO2_DEV, 0xf0, 0xef);
 147         pnp_write_config(GPIO2_DEV, 0xf1, 0xff);
 148         pnp_write_config(GPIO2_DEV, 0xf2, 0x00);
 149         pnp_write_config(GPIO2_DEV, 0xf3, 0x00);
 150         pnp_write_config(GPIO2_DEV, 0xf5, 0x48);
 151         pnp_write_config(GPIO2_DEV, 0xf6, 0x00);
 152         pnp_write_config(GPIO2_DEV, 0xf7, 0xc0);
 153         pnp_exit_ext_func_mode(GPIO2_DEV);
 154
 155         pnp_enter_ext_func_mode(GPIO3_DEV);
 156         pnp_set_logical_device(GPIO3_DEV);
 157         pnp_write_config(GPIO3_DEV, 0x30, 0x00);
 158         pnp_write_config(GPIO3_DEV, 0xf0, 0xff);
 159         pnp_write_config(GPIO3_DEV, 0xf1, 0xff);
 160         pnp_write_config(GPIO3_DEV, 0xf2, 0xff);
 161         pnp_write_config(GPIO3_DEV, 0xf3, 0x40);
 162         pnp_exit_ext_func_mode(GPIO3_DEV);
 163 }
 164
 165 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 166 {
 167   struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 168
 169         u32 bsp_apicid = 0;
 170         u32 val;
 171         u32 wants_reset;
 172         msr_t msr;
 173
 174         if (!cpu_init_detectedx && boot_cpu()) {
 175                 /* Nothing special needs to be done to find bus 0 */
 176                 /* Allow the HT devices to be found */
 177
 178                 set_bsp_node_CHtExtNodeCfgEn();
 179                 enumerate_ht_chain();
 180
 181                 sio_setup();
 182
 183                 /* Setup the mcp55 */
 184                 mcp55_enable_rom();
 185         }
 186
 187   post_code(0x30);
 188
 189         if (bist == 0) {
 190                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 191         }
 192
 193   post_code(0x32);
 194
 195         pnp_enter_ext_func_mode(SERIAL_DEV);
 196         pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
 197         w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 198         pnp_exit_ext_func_mode(SERIAL_DEV);
 199
 200         uart_init();
 201         console_init();
 202         write_GPIO();
 203         printk(BIOS_DEBUG, "\n");
 204
 205         /* Halt if there was a built in self test failure */
 206         report_bist_failure(bist);
 207
 208  val = cpuid_eax(1);
 209  printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 210  printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 211  printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
 212  printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 213
 214  /* Setup sysinfo defaults */
 215  set_sysinfo_in_ram(0);
 216
 217  update_microcode(val);
 218  post_code(0x33);
 219
 220  cpuSetAMDMSR();
 221  post_code(0x34);
 222
 223  amd_ht_init(sysinfo);
 224  post_code(0x35);
 225
 226  /* Setup nodes PCI space and start core 0 AP init. */
 227  finalize_node_setup(sysinfo);
 228
 229  /* Setup any mainboard PCI settings etc. */
 230  setup_mb_resource_map();
 231  post_code(0x36);
 232
 233  /* wait for all the APs core0 started by finalize_node_setup. */
 234  /* FIXME: A bunch of cores are going to start output to serial at once.
 235   * It would be nice to fixup prink spinlocks for ROM XIP mode.
 236   * I think it could be done by putting the spinlock flag in the cache
 237   * of the BSP located right after sysinfo.
 238   */
 239
 240         wait_all_core0_started();
 241 #if CONFIG_LOGICAL_CPUS==1
 242  /* Core0 on each node is configured. Now setup any additional cores. */
 243  printk(BIOS_DEBUG, "start_other_cores()\n");
 244         start_other_cores();
 245  post_code(0x37);
 246         wait_all_other_cores_started(bsp_apicid);
 247 #endif
 248
 249  post_code(0x38);
 250
 251 #if CONFIG_SET_FIDVID
 252  msr = rdmsr(0xc0010071);
 253  printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 254
 255  /* FIXME: The sb fid change may survive the warm reset and only
 256   * need to be done once.*/
 257
 258         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 259  post_code(0x39);
 260
 261  if (!warm_reset_detect(0)) {      // BSP is node 0
 262    init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 263  } else {
 264    init_fidvid_stage2(bsp_apicid, 0);  // BSP is node 0
 265         }
 266
 267  post_code(0x3A);
 268
 269  /* show final fid and vid */
 270  msr=rdmsr(0xc0010071);
 271  printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 272 #endif
 273
 274         init_timer(); // Need to use TMICT to synconize FID/VID
 275
 276  wants_reset = mcp55_early_setup_x();
 277
 278  /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 279  if (!warm_reset_detect(0)) {
 280    print_info("...WARM RESET...\n\n\n");
 281                 soft_reset();
 282    die("After soft_reset_x - shouldn't see this message!!!\n");
 283         }
 284
 285  if (wants_reset)
 286    printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
 287
 288  post_code(0x3B);
 289
 290 /* It's the time to set ctrl in sysinfo now; */
 291 printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 292 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 293
 294 post_code(0x3D);
 295
 296 //printk(BIOS_DEBUG, "enable_smbus()\n");
 297 //        enable_smbus(); /* enable in sio_setup */
 298
 299 post_code(0x40);
 300
 301  printk(BIOS_DEBUG, "raminit_amdmct()\n");
 302  raminit_amdmct(sysinfo);
 303  post_code(0x41);
 304
 305 // printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
 306  post_cache_as_ram();  // BSP switch stack to ram, copy then execute LB.
 307  post_code(0x42);  // Should never see this post code.
 308
 309 }
 310