src/mainboard/supermicro/h8qme_fam10/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #define FAM10_SCAN_PCI_BUS 0
  23 #define FAM10_ALLOCATE_IO_RANGE 1
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include <device/pci_def.h>
  28 #include <device/pci_ids.h>
  29 #include <arch/io.h>
  30 #include <device/pnp_def.h>
  31 #include <arch/romcc_io.h>
  32 #include <cpu/x86/lapic.h>
  33
  34 #include <console/console.h>
  35 #include <lib.h>
  36 #include <spd.h>
  37
  38 #include <cpu/amd/model_10xxx_rev.h>
  39
  40 // for enable the FAN
  41 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  42 #include "northbridge/amd/amdfam10/raminit.h"
  43 #include "northbridge/amd/amdfam10/amdfam10.h"
  44 #include "cpu/amd/model_10xxx/apic_timer.c"
  45 #include "lib/delay.c"
  46 #include "cpu/x86/lapic/boot_cpu.c"
  47 #include "northbridge/amd/amdfam10/reset_test.c"
  48 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  49 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  50
  51 #include "cpu/x86/bist.h"
  52
  53 #include "northbridge/amd/amdfam10/debug.c"
  54
  55 #include "cpu/x86/mtrr/earlymtrr.c"
  56
  57 #include "northbridge/amd/amdfam10/setup_resource_map.c"
  58
  59 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  60
  61 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  62
  63 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  64 {
  65 #define SMBUS_SWITCH1 0x70
  66 #define SMBUS_SWITCH2 0x72
  67         smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f);
  68         smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f);
  69 }
  70
  71 static inline int spd_read_byte(unsigned device, unsigned address)
  72 {
  73         return smbus_read_byte(device, address);
  74 }
  75
  76 #include "northbridge/amd/amdfam10/amdfam10.h"
  77
  78 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
  79 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
  80
  81 #include "resourcemap.c"
  82
  83 #include "cpu/amd/quadcore/quadcore.c"
  84
  85 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
  86 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
  87
  88
  89
  90 #include "cpu/amd/car/post_cache_as_ram.c"
  91
  92 #include "cpu/amd/microcode/microcode.c"
  93 #include "cpu/amd/model_10xxx/update_microcode.c"
  94 #include "cpu/amd/model_10xxx/init_cpus.c"
  95
  96
  97 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
  98 #include "northbridge/amd/amdfam10/early_ht.c"
  99
 100 static void sio_setup(void)
 101 {
 102         uint32_t dword;
 103         uint8_t byte;
 104         enable_smbus();
 105 //      smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
 106         smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
 107
 108         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 109         byte |= 0x20;
 110         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 111
 112         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 113         dword |= (1<<0);
 114         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 115
 116         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
 117         dword |= (1<<16);
 118         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 119
 120 }
 121
 122 static const u8 spd_addr[] = {
 123         //first node
 124         RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
 125 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 126         //second node
 127         RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
 128 #endif
 129 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 130         //third node
 131         RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
 132         //forth node
 133         RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
 134 #endif
 135 };
 136
 137 #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
 138 #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
 139 #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
 140 static void write_GPIO(void)
 141 {
 142         pnp_enter_ext_func_mode(GPIO1_DEV);
 143         pnp_set_logical_device(GPIO1_DEV);
 144         pnp_write_config(GPIO1_DEV, 0x30, 0x01);
 145         pnp_write_config(GPIO1_DEV, 0x60, 0x00);
 146         pnp_write_config(GPIO1_DEV, 0x61, 0x00);
 147         pnp_write_config(GPIO1_DEV, 0x62, 0x00);
 148         pnp_write_config(GPIO1_DEV, 0x63, 0x00);
 149         pnp_write_config(GPIO1_DEV, 0x70, 0x00);
 150         pnp_write_config(GPIO1_DEV, 0xf0, 0xff);
 151         pnp_write_config(GPIO1_DEV, 0xf1, 0xff);
 152         pnp_write_config(GPIO1_DEV, 0xf2, 0x00);
 153         pnp_exit_ext_func_mode(GPIO1_DEV);
 154
 155         pnp_enter_ext_func_mode(GPIO2_DEV);
 156         pnp_set_logical_device(GPIO2_DEV);
 157         pnp_write_config(GPIO2_DEV, 0x30, 0x01);
 158         pnp_write_config(GPIO2_DEV, 0xf0, 0xef);
 159         pnp_write_config(GPIO2_DEV, 0xf1, 0xff);
 160         pnp_write_config(GPIO2_DEV, 0xf2, 0x00);
 161         pnp_write_config(GPIO2_DEV, 0xf3, 0x00);
 162         pnp_write_config(GPIO2_DEV, 0xf5, 0x48);
 163         pnp_write_config(GPIO2_DEV, 0xf6, 0x00);
 164         pnp_write_config(GPIO2_DEV, 0xf7, 0xc0);
 165         pnp_exit_ext_func_mode(GPIO2_DEV);
 166
 167         pnp_enter_ext_func_mode(GPIO3_DEV);
 168         pnp_set_logical_device(GPIO3_DEV);
 169         pnp_write_config(GPIO3_DEV, 0x30, 0x00);
 170         pnp_write_config(GPIO3_DEV, 0xf0, 0xff);
 171         pnp_write_config(GPIO3_DEV, 0xf1, 0xff);
 172         pnp_write_config(GPIO3_DEV, 0xf2, 0xff);
 173         pnp_write_config(GPIO3_DEV, 0xf3, 0x40);
 174         pnp_exit_ext_func_mode(GPIO3_DEV);
 175 }
 176
 177 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 178 {
 179   struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 180
 181         u32 bsp_apicid = 0;
 182         u32 val;
 183         u32 wants_reset;
 184         msr_t msr;
 185
 186         if (!cpu_init_detectedx && boot_cpu()) {
 187                 /* Nothing special needs to be done to find bus 0 */
 188                 /* Allow the HT devices to be found */
 189
 190                 set_bsp_node_CHtExtNodeCfgEn();
 191                 enumerate_ht_chain();
 192
 193                 sio_setup();
 194
 195                 /* Setup the mcp55 */
 196                 mcp55_enable_rom();
 197         }
 198
 199   post_code(0x30);
 200
 201         if (bist == 0) {
 202                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 203         }
 204
 205   post_code(0x32);
 206
 207         pnp_enter_ext_func_mode(SERIAL_DEV);
 208         pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
 209         w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 210         pnp_exit_ext_func_mode(SERIAL_DEV);
 211
 212         uart_init();
 213         console_init();
 214         write_GPIO();
 215         printk(BIOS_DEBUG, "\n");
 216
 217         /* Halt if there was a built in self test failure */
 218         report_bist_failure(bist);
 219
 220  val = cpuid_eax(1);
 221  printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 222  printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 223  printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
 224  printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 225
 226  /* Setup sysinfo defaults */
 227  set_sysinfo_in_ram(0);
 228
 229  update_microcode(val);
 230  post_code(0x33);
 231
 232  cpuSetAMDMSR();
 233  post_code(0x34);
 234
 235  amd_ht_init(sysinfo);
 236  post_code(0x35);
 237
 238  /* Setup nodes PCI space and start core 0 AP init. */
 239  finalize_node_setup(sysinfo);
 240
 241  /* Setup any mainboard PCI settings etc. */
 242  setup_mb_resource_map();
 243  post_code(0x36);
 244
 245  /* wait for all the APs core0 started by finalize_node_setup. */
 246  /* FIXME: A bunch of cores are going to start output to serial at once.
 247   * It would be nice to fixup prink spinlocks for ROM XIP mode.
 248   * I think it could be done by putting the spinlock flag in the cache
 249   * of the BSP located right after sysinfo.
 250   */
 251
 252         wait_all_core0_started();
 253 #if CONFIG_LOGICAL_CPUS==1
 254  /* Core0 on each node is configured. Now setup any additional cores. */
 255  printk(BIOS_DEBUG, "start_other_cores()\n");
 256         start_other_cores();
 257  post_code(0x37);
 258         wait_all_other_cores_started(bsp_apicid);
 259 #endif
 260
 261  post_code(0x38);
 262
 263 #if CONFIG_SET_FIDVID
 264  msr = rdmsr(0xc0010071);
 265  printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 266
 267  /* FIXME: The sb fid change may survive the warm reset and only
 268   * need to be done once.*/
 269
 270         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 271  post_code(0x39);
 272
 273  if (!warm_reset_detect(0)) {      // BSP is node 0
 274    init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 275  } else {
 276    init_fidvid_stage2(bsp_apicid, 0);  // BSP is node 0
 277         }
 278
 279  post_code(0x3A);
 280
 281  /* show final fid and vid */
 282  msr=rdmsr(0xc0010071);
 283  printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 284 #endif
 285
 286         init_timer(); // Need to use TMICT to synconize FID/VID
 287
 288  wants_reset = mcp55_early_setup_x();
 289
 290  /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 291  if (!warm_reset_detect(0)) {
 292    print_info("...WARM RESET...\n\n\n");
 293                 soft_reset();
 294    die("After soft_reset_x - shouldn't see this message!!!\n");
 295         }
 296
 297  if (wants_reset)
 298    printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
 299
 300  post_code(0x3B);
 301
 302 /* It's the time to set ctrl in sysinfo now; */
 303 printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 304 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 305
 306 post_code(0x3D);
 307
 308 //printk(BIOS_DEBUG, "enable_smbus()\n");
 309 //        enable_smbus(); /* enable in sio_setup */
 310
 311 post_code(0x40);
 312
 313  printk(BIOS_DEBUG, "raminit_amdmct()\n");
 314  raminit_amdmct(sysinfo);
 315  post_code(0x41);
 316
 317 // printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
 318  post_cache_as_ram();  // BSP switch stack to ram, copy then execute LB.
 319  post_code(0x42);  // Should never see this post code.
 320
 321 }
 322