2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <console/console.h>
23 #include <arch/smp/mpspec.h>
24 #include <device/pci.h>
27 #include <cpu/amd/amdfam10_sysconf.h>
28 #include "mb_sysconf.h"
30 extern unsigned sbdn3;
32 static void *smp_write_config_table(void *v)
34 struct mp_config_table *mc;
35 struct mb_sysconf_t *m;
39 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
41 mptable_init(mc, LOCAL_APIC_ADDR);
43 smp_write_processors(mc);
49 mptable_write_buses(mc, NULL, &bus_isa);
51 /*I/O APICs: APIC ID Version State Address*/
57 dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
59 res = find_resource(dev, PCI_BASE_ADDRESS_1);
61 smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
65 pci_write_config32(dev, 0x7c, dword);
68 pci_write_config32(dev, 0x80, dword);
71 pci_write_config32(dev, 0x84, dword);
78 mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
80 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0xb); /* 11 USB, OK */
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0xa); /* 10 USB, OK */
84 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x5); /* 5 IDE, OK*/
85 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
87 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0xa); /* 10 VGA, OK*/
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/
90 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/
93 if(!m->bus_mcp55[j]) continue;
95 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
101 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
104 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
105 mptable_lintsrc(mc, bus_isa);
106 /* There is no extension information... */
108 /* Compute the checksums */
109 return mptable_finalize(mc);
112 unsigned long write_smp_table(unsigned long addr)
115 v = smp_write_floating_table(addr, 0);
116 return (unsigned long)smp_write_config_table(v);