2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <arch/romcc_io.h>
25 #include <device/pci_ids.h>
27 AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
28 #define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
30 /* SP5100 GPIO 53-56 contoled by SMBUS PCI_Reg 0x52 */
31 #define SP5100_GPIO53_56 0x52
34 * TODO not support all GPIO yet
35 * @param reg -GPIO Cntrl Register
36 * @param out -GPIO bitmap
37 * @param out -GPIO enable bitmap
39 static void sp5100_set_gpio(u8 reg, u8 out, u8 enable)
42 device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
44 value = pci_read_config8(sm_dev, reg);
47 value &= ~(enable << 4);
48 pci_write_config8(sm_dev, reg, value);
51 /*-----------------------------------------------------------------------------
53 * SPD address table - porting required
55 static const UINT8 spdAddressLookup [8] [4] [2] = { // socket, channel, dimm
86 /*-----------------------------------------------------------------------------
88 * readSmbusByteData - read a single SPD byte from any offset
91 static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
96 address |= 1; // set read bit
98 outb(0xFF, iobase + 0); // clear error status
99 outb(0x1F, iobase + 1); // clear error status
100 outb(offset, iobase + 3); // offset in eeprom
101 outb(address, iobase + 4); // slave address and read bit
102 outb(0x48, iobase + 2); // read byte command
104 // time limit to avoid hanging for unexpected error status (should never happen)
105 limit = __rdtsc () + 2000000000 / 10;
108 status = inb(iobase);
109 if (__rdtsc () > limit) break;
110 if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
111 if ((status & 1) == 1) continue; // HostBusy set, keep waiting
115 buffer [0] = inb(iobase + 5);
116 if (status == 2) status = 0; // check for done with no errors
120 /*-----------------------------------------------------------------------------
122 * readSmbusByte - read a single SPD byte from the default offset
123 * this function is faster function readSmbusByteData
126 static int readSmbusByte (int iobase, int address, char *buffer)
131 outb(0xFF, iobase + 0); // clear error status
132 outb(0x44, iobase + 2); // read command
134 // time limit to avoid hanging for unexpected error status
135 limit = __rdtsc () + 2000000000 / 10;
138 status = inb(iobase);
139 if (__rdtsc () > limit) break;
140 if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
141 if ((status & 1) == 1) continue; // HostBusy set, keep waiting
145 buffer [0] = inb(iobase + 5);
146 if (status == 2) status = 0; // check for done with no errors
150 /*---------------------------------------------------------------------------
152 * readspd - Read one or more SPD bytes from a DIMM.
153 * Start with offset zero and read sequentially.
154 * Optimization relies on autoincrement to avoid
155 * sending offset for every byte.
156 * Reads 128 bytes in 7-8 ms at 400 KHz.
159 static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
163 /* read the first byte using offset zero */
164 error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
169 /* read the remaining bytes using auto-increment for speed */
170 for (index = 1; index < count; index++)
172 error = readSmbusByte (iobase, SmbusSlaveAddress, buffer + index);
180 static void writePmReg (int reg, int data)
186 static void setupFch (int ioBase)
188 writePmReg (0x2D, ioBase >> 8);
189 writePmReg (0x2C, ioBase | 1);
190 writePmReg (0x29, 0x80);
191 writePmReg (0x28, 0x61);
192 outb(66000000 / 400000 / 4, ioBase + 0x0E); // set SMBus clock to 400 KHz
195 AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
197 int spdAddress, ioBase;
201 if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR;
202 if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR;
203 if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
204 i2c_channel = (UINT8) info->SocketId;
206 /* set ght i2c channel
207 * GPIO54,53 control the HC4052 S1,S0
209 * 0 0 channel 1 (Socket1)
210 * 0 1 channel 2 (Socket2)
211 * 1 0 channel 3 (Socket3)
212 * 1 1 channel 4 (Socket4)
214 sp5100_set_gpio(SP5100_GPIO53_56, i2c_channel, 0x03);
216 spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
221 * SMBus Base Address was set during southbridge early setup.
222 * e.g. sb700 IO mapped SMBUS_IO_BASE 0x6000
224 sm_dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM), 0);
225 ioBase = pci_read_config32(sm_dev, 0x90) & (0xFFFFFFF0);
228 return readspd(ioBase, spdAddress, (void *)info->Buffer, 256);