src/mainboard/supermicro/h8dmr/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #if CONFIG_K8_REV_F_SUPPORT == 1
  23 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  24 #endif
  25
  26 #include <stdint.h>
  27 #include <string.h>
  28 #include <device/pci_def.h>
  29 #include <device/pci_ids.h>
  30 #include <arch/io.h>
  31 #include <device/pnp_def.h>
  32 #include <arch/romcc_io.h>
  33 #include <cpu/x86/lapic.h>
  34 #include <pc80/mc146818rtc.h>
  35
  36 #include <console/console.h>
  37 #include <lib.h>
  38 #include <spd.h>
  39
  40 #include <cpu/amd/model_fxx_rev.h>
  41
  42 // for enable the FAN
  43 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  44 #include "northbridge/amd/amdk8/raminit.h"
  45 #include "cpu/amd/model_fxx/apic_timer.c"
  46 #include "lib/delay.c"
  47
  48 #include "cpu/x86/lapic/boot_cpu.c"
  49 #include "northbridge/amd/amdk8/reset_test.c"
  50 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  51 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  52
  53 #include "cpu/x86/bist.h"
  54
  55 #include "northbridge/amd/amdk8/debug.c"
  56
  57 #include "cpu/x86/mtrr/earlymtrr.c"
  58
  59 #include "northbridge/amd/amdk8/setup_resource_map.c"
  60
  61 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  62
  63 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  64
  65 static void memreset(int controllers, const struct mem_controller *ctrl)
  66 {
  67 }
  68
  69 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  70 {
  71         /* nothing to do */
  72 }
  73
  74 static inline int spd_read_byte(unsigned device, unsigned address)
  75 {
  76         return smbus_read_byte(device, address);
  77 }
  78
  79 #include "northbridge/amd/amdk8/amdk8_f.h"
  80 #include "northbridge/amd/amdk8/incoherent_ht.c"
  81 #include "northbridge/amd/amdk8/coherent_ht.c"
  82 #include "northbridge/amd/amdk8/raminit_f.c"
  83 #include "lib/generic_sdram.c"
  84
  85 #include "resourcemap.c"
  86
  87 #include "cpu/amd/dualcore/dualcore.c"
  88
  89 #define MCP55_PCI_E_X_0 4
  90
  91 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
  92 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
  93
  94 #include "cpu/amd/car/post_cache_as_ram.c"
  95
  96 #include "cpu/amd/model_fxx/init_cpus.c"
  97
  98 #include "cpu/amd/model_fxx/fidvid.c"
  99
 100 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 101 #include "northbridge/amd/amdk8/early_ht.c"
 102
 103 static void sio_setup(void)
 104 {
 105         uint32_t dword;
 106         uint8_t byte;
 107         enable_smbus();
 108 //      smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
 109         smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
 110
 111         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 112         byte |= 0x20;
 113         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 114
 115         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 116         dword |= (1<<0);
 117         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 118
 119         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
 120         dword |= (1<<16);
 121         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 122 }
 123
 124 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 125 {
 126         static const uint16_t spd_addr [] = {
 127                         // Node 0
 128                         DIMM0, DIMM2, 0, 0,
 129                         DIMM1, DIMM3, 0, 0,
 130                         // Node 1
 131                         DIMM4, DIMM6, 0, 0,
 132                         DIMM5, DIMM7, 0, 0,
 133         };
 134
 135         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 136                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 137
 138         int needs_reset = 0;
 139         unsigned bsp_apicid = 0;
 140
 141         if (!cpu_init_detectedx && boot_cpu()) {
 142                 /* Nothing special needs to be done to find bus 0 */
 143                 /* Allow the HT devices to be found */
 144
 145                 enumerate_ht_chain();
 146
 147                 sio_setup();
 148
 149                 /* Setup the mcp55 */
 150                 mcp55_enable_rom();
 151         }
 152
 153         if (bist == 0) {
 154                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 155         }
 156
 157         pnp_enter_ext_func_mode(SERIAL_DEV);
 158         pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
 159         w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 160         pnp_exit_ext_func_mode(SERIAL_DEV);
 161
 162         uart_init();
 163         console_init();
 164
 165         /* Halt if there was a built in self test failure */
 166         report_bist_failure(bist);
 167
 168         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 169
 170         setup_mb_resource_map();
 171
 172         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 173
 174 #if CONFIG_MEM_TRAIN_SEQ == 1
 175         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 176 #endif
 177         setup_coherent_ht_domain(); // routing table and start other core0
 178
 179         wait_all_core0_started();
 180 #if CONFIG_LOGICAL_CPUS==1
 181         // It is said that we should start core1 after all core0 launched
 182         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 183          * So here need to make sure last core0 is started, esp for two way system,
 184          * (there may be apic id conflicts in that case)
 185          */
 186         start_other_cores();
 187         wait_all_other_cores_started(bsp_apicid);
 188 #endif
 189
 190         /* it will set up chains and store link pair for optimization later */
 191         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 192
 193 #if CONFIG_SET_FIDVID
 194         {
 195                 msr_t msr;
 196                 msr=rdmsr(0xc0010042);
 197                 printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo);
 198         }
 199
 200         enable_fid_change();
 201
 202         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 203
 204         init_fidvid_bsp(bsp_apicid);
 205
 206         // show final fid and vid
 207         {
 208                 msr_t msr;
 209                 msr=rdmsr(0xc0010042);
 210                 printk(BIOS_DEBUG, "end   msr fid, vid %08x, %08x\n", msr.hi, msr.lo);
 211         }
 212 #endif
 213
 214         init_timer(); // Need to use TMICT to synconize FID/VID
 215
 216         needs_reset |= optimize_link_coherent_ht();
 217         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 218         needs_reset |= mcp55_early_setup_x();
 219
 220         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 221         if (needs_reset) {
 222                 print_info("ht reset -\n");
 223                 soft_reset();
 224         }
 225
 226         allow_all_aps_stop(bsp_apicid);
 227
 228         //It's the time to set ctrl in sysinfo now;
 229         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 230
 231 //        enable_smbus(); /* enable in sio_setup */
 232
 233         /* all ap stopped? */
 234
 235         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 236
 237         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 238 }