src/mainboard/supermicro/h8dmr/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #if CONFIG_K8_REV_F_SUPPORT == 1
  23 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  24 #endif
  25
  26 #include <stdint.h>
  27 #include <string.h>
  28 #include <device/pci_def.h>
  29 #include <device/pci_ids.h>
  30 #include <arch/io.h>
  31 #include <device/pnp_def.h>
  32 #include <arch/romcc_io.h>
  33 #include <cpu/x86/lapic.h>
  34 #include <pc80/mc146818rtc.h>
  35
  36 #include <console/console.h>
  37 #include <lib.h>
  38 #include <spd.h>
  39
  40 #include <cpu/amd/model_fxx_rev.h>
  41
  42 // for enable the FAN
  43 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  44 #include "northbridge/amd/amdk8/raminit.h"
  45 #include "cpu/amd/model_fxx/apic_timer.c"
  46 #include "lib/delay.c"
  47
  48 #include "cpu/x86/lapic/boot_cpu.c"
  49 #include "northbridge/amd/amdk8/reset_test.c"
  50 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  51 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  52
  53 #include "cpu/x86/bist.h"
  54
  55 #include "northbridge/amd/amdk8/debug.c"
  56
  57 #include "cpu/x86/mtrr/earlymtrr.c"
  58
  59 #include "northbridge/amd/amdk8/setup_resource_map.c"
  60
  61 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  62
  63 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  64
  65 static void memreset(int controllers, const struct mem_controller *ctrl)
  66 {
  67 }
  68
  69 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  70 {
  71         /* nothing to do */
  72 }
  73
  74 static inline int spd_read_byte(unsigned device, unsigned address)
  75 {
  76         return smbus_read_byte(device, address);
  77 }
  78
  79 #include "northbridge/amd/amdk8/amdk8_f.h"
  80 #include "northbridge/amd/amdk8/incoherent_ht.c"
  81 #include "northbridge/amd/amdk8/coherent_ht.c"
  82 #include "northbridge/amd/amdk8/raminit_f.c"
  83 #include "lib/generic_sdram.c"
  84
  85 #include "resourcemap.c"
  86
  87 #include "cpu/amd/dualcore/dualcore.c"
  88
  89 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
  90 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
  91
  92 #include "cpu/amd/car/post_cache_as_ram.c"
  93
  94 #include "cpu/amd/model_fxx/init_cpus.c"
  95
  96 #include "cpu/amd/model_fxx/fidvid.c"
  97
  98 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
  99 #include "northbridge/amd/amdk8/early_ht.c"
 100
 101 static void sio_setup(void)
 102 {
 103         uint32_t dword;
 104         uint8_t byte;
 105         enable_smbus();
 106 //      smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
 107         smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
 108
 109         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 110         byte |= 0x20;
 111         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 112
 113         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 114         dword |= (1<<0);
 115         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 116
 117         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
 118         dword |= (1<<16);
 119         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 120 }
 121
 122 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 123 {
 124         static const uint16_t spd_addr [] = {
 125                         // Node 0
 126                         DIMM0, DIMM2, 0, 0,
 127                         DIMM1, DIMM3, 0, 0,
 128                         // Node 1
 129                         DIMM4, DIMM6, 0, 0,
 130                         DIMM5, DIMM7, 0, 0,
 131         };
 132
 133         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 134                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 135
 136         int needs_reset = 0;
 137         unsigned bsp_apicid = 0;
 138
 139         if (!cpu_init_detectedx && boot_cpu()) {
 140                 /* Nothing special needs to be done to find bus 0 */
 141                 /* Allow the HT devices to be found */
 142
 143                 enumerate_ht_chain();
 144
 145                 sio_setup();
 146
 147                 /* Setup the mcp55 */
 148                 mcp55_enable_rom();
 149         }
 150
 151         if (bist == 0) {
 152                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 153         }
 154
 155         pnp_enter_ext_func_mode(SERIAL_DEV);
 156         pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
 157         w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 158         pnp_exit_ext_func_mode(SERIAL_DEV);
 159
 160         uart_init();
 161         console_init();
 162
 163         /* Halt if there was a built in self test failure */
 164         report_bist_failure(bist);
 165
 166         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 167
 168         setup_mb_resource_map();
 169
 170         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 171
 172 #if CONFIG_MEM_TRAIN_SEQ == 1
 173         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 174 #endif
 175         setup_coherent_ht_domain(); // routing table and start other core0
 176
 177         wait_all_core0_started();
 178 #if CONFIG_LOGICAL_CPUS==1
 179         // It is said that we should start core1 after all core0 launched
 180         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 181          * So here need to make sure last core0 is started, esp for two way system,
 182          * (there may be apic id conflicts in that case)
 183          */
 184         start_other_cores();
 185         wait_all_other_cores_started(bsp_apicid);
 186 #endif
 187
 188         /* it will set up chains and store link pair for optimization later */
 189         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 190
 191 #if CONFIG_SET_FIDVID
 192         {
 193                 msr_t msr;
 194                 msr=rdmsr(0xc0010042);
 195                 printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo);
 196         }
 197
 198         enable_fid_change();
 199
 200         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 201
 202         init_fidvid_bsp(bsp_apicid);
 203
 204         // show final fid and vid
 205         {
 206                 msr_t msr;
 207                 msr=rdmsr(0xc0010042);
 208                 printk(BIOS_DEBUG, "end   msr fid, vid %08x, %08x\n", msr.hi, msr.lo);
 209         }
 210 #endif
 211
 212         init_timer(); // Need to use TMICT to synconize FID/VID
 213
 214         needs_reset |= optimize_link_coherent_ht();
 215         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 216         needs_reset |= mcp55_early_setup_x();
 217
 218         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 219         if (needs_reset) {
 220                 print_info("ht reset -\n");
 221                 soft_reset();
 222         }
 223
 224         allow_all_aps_stop(bsp_apicid);
 225
 226         //It's the time to set ctrl in sysinfo now;
 227         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 228
 229 //        enable_smbus(); /* enable in sio_setup */
 230
 231         /* all ap stopped? */
 232
 233         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 234
 235         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 236 }