src/mainboard/supermicro/h8dme/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  17  */
  18
  19 #if CONFIG_K8_REV_F_SUPPORT == 1
  20 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  21 #endif
  22
  23 #include <stdint.h>
  24 #include <string.h>
  25 #include <device/pci_def.h>
  26 #include <device/pci_ids.h>
  27 #include <arch/io.h>
  28 #include <device/pnp_def.h>
  29 #include <arch/romcc_io.h>
  30 #include <cpu/x86/lapic.h>
  31 #include <pc80/mc146818rtc.h>
  32 #include <console/console.h>
  33 #include <lib.h>
  34 #include <spd.h>
  35 #include <cpu/amd/model_fxx_rev.h>
  36 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
  37 #include "northbridge/amd/amdk8/raminit.h"
  38 #include "cpu/amd/model_fxx/apic_timer.c"
  39 #include "lib/delay.c"
  40 #include "cpu/x86/lapic/boot_cpu.c"
  41 #include "northbridge/amd/amdk8/reset_test.c"
  42 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  43 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  44 #include "cpu/x86/bist.h"
  45 #include "northbridge/amd/amdk8/debug.c"
  46 #include "cpu/x86/mtrr/earlymtrr.c"
  47 #include "northbridge/amd/amdk8/setup_resource_map.c"
  48 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  49
  50 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  51
  52 static void memreset(int controllers, const struct mem_controller *ctrl)
  53 {
  54 }
  55
  56 static inline void dump_smbus_registers(void)
  57 {
  58         u32 device;
  59
  60         print_debug("\n");
  61         for (device = 1; device < 0x80; device++) {
  62                 int j;
  63                 if (smbus_read_byte(device, 0) < 0)
  64                         continue;
  65                 printk(BIOS_DEBUG, "smbus: %02x", device);
  66                 for (j = 0; j < 256; j++) {
  67                         int status;
  68                         unsigned char byte;
  69                         status = smbus_read_byte(device, j);
  70                         if (status < 0) {
  71                                 break;
  72                         }
  73                         if ((j & 0xf) == 0) {
  74                                 printk(BIOS_DEBUG, "\n%02x: ", j);
  75                         }
  76                         byte = status & 0xff;
  77                         printk(BIOS_DEBUG, "%02x ", byte);
  78                 }
  79                 print_debug("\n");
  80         }
  81 }
  82
  83 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  84 {
  85 #if 0
  86 /* We don't do any switching yet. */
  87 #define SMBUS_SWITCH1 0x48
  88 #define SMBUS_SWITCH2 0x49
  89         unsigned device=(ctrl->channel0[0])>>8;
  90         smbus_send_byte(SMBUS_SWITCH1, device);
  91         smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
  92 #endif
  93 }
  94
  95 #if 0
  96 static int smbus_send_byte_one(unsigned device, unsigned char val)
  97 {
  98         return do_smbus_send_byte(SMBUS1_IO_BASE, device, val);
  99 }
 100
 101 static inline void change_i2c_mux(unsigned device)
 102 {
 103 #define SMBUS_SWITCH1 0x48
 104 #define SMBUS_SWITHC2 0x49
 105         smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
 106         smbus_send_byte_one(SMBUS_SWITCH2, (device >> 4) & 0x0f);
 107         int ret;
 108         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
 109         dump_smbus_registers();
 110         ret = smbus_send_byte(SMBUS_SWITCH1, device);
 111         print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
 112         dump_smbus_registers();
 113         ret = smbus_send_byte_one(SMBUS_SWITCH2, device);
 114         print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
 115         dump_smbus_registers();
 116 }
 117 #endif
 118
 119 static inline int spd_read_byte(unsigned device, unsigned address)
 120 {
 121         return smbus_read_byte(device, address);
 122 }
 123
 124 #include "northbridge/amd/amdk8/amdk8_f.h"
 125 #include "northbridge/amd/amdk8/incoherent_ht.c"
 126 #include "northbridge/amd/amdk8/coherent_ht.c"
 127 #include "northbridge/amd/amdk8/raminit_f.c"
 128 #include "lib/generic_sdram.c"
 129 #include "resourcemap.c"
 130 #include "cpu/amd/dualcore/dualcore.c"
 131 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 132 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 133 #include "cpu/amd/car/post_cache_as_ram.c"
 134 #include "cpu/amd/model_fxx/init_cpus.c"
 135 #include "cpu/amd/model_fxx/fidvid.c"
 136 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 137 #include "northbridge/amd/amdk8/early_ht.c"
 138
 139 static void sio_setup(void)
 140 {
 141         uint32_t dword;
 142         uint8_t byte;
 143
 144         enable_smbus();
 145 //      smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
 146         smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff);  /* set FAN ctrl to DC mode */
 147
 148         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b);
 149         byte |= 0x20;
 150         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte);
 151
 152         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0);
 153         dword |= (1 << 0);
 154         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword);
 155
 156         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
 157         dword |= (1 << 16);
 158         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
 159 }
 160
 161 /* We have no idea where the SMBUS switch is. This doesn't do anything ATM. */
 162 #define RC0 (2<<8)
 163 #define RC1 (1<<8)
 164
 165 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 166 {
 167 /* The SPD is being read from the CPU1 (marked CPU2 on the board) and we
 168    don't know how to switch the SMBus to decode the CPU0 SPDs. So, The
 169    memory on each CPU must be an exact match.
 170  */
 171         static const uint16_t spd_addr[] = {
 172                 // Node 0
 173                 RC0 | DIMM0, RC0 | DIMM2,
 174                 RC0 | DIMM4, RC0 | DIMM6,
 175                 RC0 | DIMM1, RC0 | DIMM3,
 176                 RC0 | DIMM5, RC0 | DIMM7,
 177                 // Node 1
 178                 RC1 | DIMM0, RC1 | DIMM2,
 179                 RC1 | DIMM4, RC1 | DIMM6,
 180                 RC1 | DIMM1, RC1 | DIMM3,
 181                 RC1 | DIMM5, RC1 | DIMM7,
 182         };
 183
 184         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 185                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 186
 187         int needs_reset = 0;
 188         unsigned bsp_apicid = 0;
 189
 190         if (!cpu_init_detectedx && boot_cpu()) {
 191                 /* Nothing special needs to be done to find bus 0 */
 192                 /* Allow the HT devices to be found */
 193
 194                 enumerate_ht_chain();
 195
 196                 sio_setup();
 197
 198                 /* Setup the mcp55 */
 199                 mcp55_enable_rom();
 200         }
 201
 202         if (bist == 0) {
 203                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 204         }
 205
 206         pnp_enter_ext_func_mode(SERIAL_DEV);
 207         pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
 208         w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 209         pnp_exit_ext_func_mode(SERIAL_DEV);
 210
 211         uart_init();
 212         console_init();
 213
 214         /* Halt if there was a built in self test failure */
 215         report_bist_failure(bist);
 216
 217         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 218
 219         setup_mb_resource_map();
 220
 221         print_debug("bsp_apicid=");
 222         print_debug_hex8(bsp_apicid);
 223         print_debug("\n");
 224
 225 #if CONFIG_MEM_TRAIN_SEQ == 1
 226         set_sysinfo_in_ram(0);  // in BSP so could hold all ap until sysinfo is in ram
 227 #endif
 228 /*      dump_smbus_registers(); */
 229         setup_coherent_ht_domain();     // routing table and start other core0
 230
 231         wait_all_core0_started();
 232 #if CONFIG_LOGICAL_CPUS==1
 233         // It is said that we should start core1 after all core0 launched
 234         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 235          * So here need to make sure last core0 is started, esp for two way system,
 236          * (there may be apic id conflicts in that case)
 237          */
 238         start_other_cores();
 239         wait_all_other_cores_started(bsp_apicid);
 240 #endif
 241
 242         /* it will set up chains and store link pair for optimization later */
 243         ht_setup_chains_x(sysinfo);     // it will init sblnk and sbbusn, nodes, sbdn
 244
 245 #if CONFIG_SET_FIDVID
 246
 247         {
 248                 msr_t msr;
 249                 msr = rdmsr(0xc0010042);
 250                 print_debug("begin msr fid, vid ");
 251                 print_debug_hex32(msr.hi);
 252                 print_debug_hex32(msr.lo);
 253                 print_debug("\n");
 254
 255         }
 256
 257         enable_fid_change();
 258
 259         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 260
 261         init_fidvid_bsp(bsp_apicid);
 262
 263         // show final fid and vid
 264         {
 265                 msr_t msr;
 266                 msr = rdmsr(0xc0010042);
 267                 print_debug("end   msr fid, vid ");
 268                 print_debug_hex32(msr.hi);
 269                 print_debug_hex32(msr.lo);
 270                 print_debug("\n");
 271
 272         }
 273 #endif
 274
 275         init_timer(); /* Need to use TMICT to synconize FID/VID. */
 276
 277         needs_reset |= optimize_link_coherent_ht();
 278         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 279         needs_reset |= mcp55_early_setup_x();
 280
 281         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 282         if (needs_reset) {
 283                 print_info("ht reset -\n");
 284                 soft_reset();
 285         }
 286
 287         allow_all_aps_stop(bsp_apicid);
 288
 289         //It's the time to set ctrl in sysinfo now;
 290         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 291
 292         enable_smbus();         /* enable in sio_setup */
 293
 294         /* all ap stopped? */
 295
 296         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 297
 298         post_cache_as_ram();    // bsp swtich stack to ram and copy sysinfo ram now
 299 }