src/mainboard/supermicro/h8dme/resourcemap.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 static void setup_mb_resource_map(void)
  23 {
  24         static const unsigned int register_values[] = {
  25                 /* Careful set limit registers before base registers which contain the enables */
  26                 /* DRAM Limit i Registers
  27                  * F1:0x44 i = 0
  28                  * F1:0x4C i = 1
  29                  * F1:0x54 i = 2
  30                  * F1:0x5C i = 3
  31                  * F1:0x64 i = 4
  32                  * F1:0x6C i = 5
  33                  * F1:0x74 i = 6
  34                  * F1:0x7C i = 7
  35                  * [ 2: 0] Destination Node ID
  36                  *         000 = Node 0
  37                  *         001 = Node 1
  38                  *         010 = Node 2
  39                  *         011 = Node 3
  40                  *         100 = Node 4
  41                  *         101 = Node 5
  42                  *         110 = Node 6
  43                  *         111 = Node 7
  44                  * [ 7: 3] Reserved
  45                  * [10: 8] Interleave select
  46                  *         specifies the values of A[14:12] to use with interleave enable.
  47                  * [15:11] Reserved
  48                  * [31:16] DRAM Limit Address i Bits 39-24
  49                  *         This field defines the upper address bits of a 40 bit  address
  50                  *         that define the end of the DRAM region.
  51                  */
  52                 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
  53                 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
  54                 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
  55                 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
  56                 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
  57                 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
  58                 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
  59                 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
  60
  61                 /* DRAM Base i Registers
  62                  * F1:0x40 i = 0
  63                  * F1:0x48 i = 1
  64                  * F1:0x50 i = 2
  65                  * F1:0x58 i = 3
  66                  * F1:0x60 i = 4
  67                  * F1:0x68 i = 5
  68                  * F1:0x70 i = 6
  69                  * F1:0x78 i = 7
  70                  * [ 0: 0] Read Enable
  71                  *         0 = Reads Disabled
  72                  *         1 = Reads Enabled
  73                  * [ 1: 1] Write Enable
  74                  *         0 = Writes Disabled
  75                  *         1 = Writes Enabled
  76                  * [ 7: 2] Reserved
  77                  * [10: 8] Interleave Enable
  78                  *         000 = No interleave
  79                  *         001 = Interleave on A[12] (2 nodes)
  80                  *         010 = reserved
  81                  *         011 = Interleave on A[12] and A[14] (4 nodes)
  82                  *         100 = reserved
  83                  *         101 = reserved
  84                  *         110 = reserved
  85                  *         111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
  86                  * [15:11] Reserved
  87                  * [13:16] DRAM Base Address i Bits 39-24
  88                  *         This field defines the upper address bits of a 40-bit address
  89                  *         that define the start of the DRAM region.
  90                  */
  91                 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
  92                 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
  93                 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
  94                 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
  95                 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
  96                 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
  97                 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
  98                 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
  99
 100                 /* Memory-Mapped I/O Limit i Registers
 101                  * F1:0x84 i = 0
 102                  * F1:0x8C i = 1
 103                  * F1:0x94 i = 2
 104                  * F1:0x9C i = 3
 105                  * F1:0xA4 i = 4
 106                  * F1:0xAC i = 5
 107                  * F1:0xB4 i = 6
 108                  * F1:0xBC i = 7
 109                  * [ 2: 0] Destination Node ID
 110                  *         000 = Node 0
 111                  *         001 = Node 1
 112                  *         010 = Node 2
 113                  *         011 = Node 3
 114                  *         100 = Node 4
 115                  *         101 = Node 5
 116                  *         110 = Node 6
 117                  *         111 = Node 7
 118                  * [ 3: 3] Reserved
 119                  * [ 5: 4] Destination Link ID
 120                  *         00 = Link 0
 121                  *         01 = Link 1
 122                  *         10 = Link 2
 123                  *         11 = Reserved
 124                  * [ 6: 6] Reserved
 125                  * [ 7: 7] Non-Posted
 126                  *         0 = CPU writes may be posted
 127                  *         1 = CPU writes must be non-posted
 128                  * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
 129                  *         This field defines the upp adddress bits of a 40-bit address that
 130                  *         defines the end of a memory-mapped I/O region n
 131                  */
 132                 PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
 133                 PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
 134                 PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
 135                 PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
 136                 PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
 137                 PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
 138                 PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
 139 //              PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
 140
 141                 /* Memory-Mapped I/O Base i Registers
 142                  * F1:0x80 i = 0
 143                  * F1:0x88 i = 1
 144                  * F1:0x90 i = 2
 145                  * F1:0x98 i = 3
 146                  * F1:0xA0 i = 4
 147                  * F1:0xA8 i = 5
 148                  * F1:0xB0 i = 6
 149                  * F1:0xB8 i = 7
 150                  * [ 0: 0] Read Enable
 151                  *         0 = Reads disabled
 152                  *         1 = Reads Enabled
 153                  * [ 1: 1] Write Enable
 154                  *         0 = Writes disabled
 155                  *         1 = Writes Enabled
 156                  * [ 2: 2] Cpu Disable
 157                  *         0 = Cpu can use this I/O range
 158                  *         1 = Cpu requests do not use this I/O range
 159                  * [ 3: 3] Lock
 160                  *         0 = base/limit registers i are read/write
 161                  *         1 = base/limit registers i are read-only
 162                  * [ 7: 4] Reserved
 163                  * [31: 8] Memory-Mapped I/O Base Address i (39-16)
 164                  *         This field defines the upper address bits of a 40bit address
 165                  *         that defines the start of memory-mapped I/O region i
 166                  */
 167                 PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
 168                 PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
 169                 PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
 170                 PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
 171                 PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
 172                 PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
 173                 PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
 174 //              PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
 175
 176                 /* PCI I/O Limit i Registers
 177                  * F1:0xC4 i = 0
 178                  * F1:0xCC i = 1
 179                  * F1:0xD4 i = 2
 180                  * F1:0xDC i = 3
 181                  * [ 2: 0] Destination Node ID
 182                  *         000 = Node 0
 183                  *         001 = Node 1
 184                  *         010 = Node 2
 185                  *         011 = Node 3
 186                  *         100 = Node 4
 187                  *         101 = Node 5
 188                  *         110 = Node 6
 189                  *         111 = Node 7
 190                  * [ 3: 3] Reserved
 191                  * [ 5: 4] Destination Link ID
 192                  *         00 = Link 0
 193                  *         01 = Link 1
 194                  *         10 = Link 2
 195                  *         11 = reserved
 196                  * [11: 6] Reserved
 197                  * [24:12] PCI I/O Limit Address i
 198                  *         This field defines the end of PCI I/O region n
 199                  * [31:25] Reserved
 200                  */
 201                 PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
 202                 PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset
 203                 PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
 204                 PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
 205
 206                 /* PCI I/O Base i Registers
 207                  * F1:0xC0 i = 0
 208                  * F1:0xC8 i = 1
 209                  * F1:0xD0 i = 2
 210                  * F1:0xD8 i = 3
 211                  * [ 0: 0] Read Enable
 212                  *         0 = Reads Disabled
 213                  *         1 = Reads Enabled
 214                  * [ 1: 1] Write Enable
 215                  *         0 = Writes Disabled
 216                  *         1 = Writes Enabled
 217                  * [ 3: 2] Reserved
 218                  * [ 4: 4] VGA Enable
 219                  *         0 = VGA matches Disabled
 220                  *         1 = matches all address < 64K and where A[9:0] is in the
 221                  *             range 3B0-3BB or 3C0-3DF independen of the base & limit registers
 222                  * [ 5: 5] ISA Enable
 223                  *         0 = ISA matches Disabled
 224                  *         1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
 225                  *             from matching agains this base/limit pair
 226                  * [11: 6] Reserved
 227                  * [24:12] PCI I/O Base i
 228                  *         This field defines the start of PCI I/O region n
 229                  * [31:25] Reserved
 230                  */
 231                 PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
 232                 PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
 233                 PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
 234                 PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
 235
 236                 /* Config Base and Limit i Registers
 237                  * F1:0xE0 i = 0
 238                  * F1:0xE4 i = 1
 239                  * F1:0xE8 i = 2
 240                  * F1:0xEC i = 3
 241                  * [ 0: 0] Read Enable
 242                  *         0 = Reads Disabled
 243                  *         1 = Reads Enabled
 244                  * [ 1: 1] Write Enable
 245                  *         0 = Writes Disabled
 246                  *         1 = Writes Enabled
 247                  * [ 2: 2] Device Number Compare Enable
 248                  *         0 = The ranges are based on bus number
 249                  *         1 = The ranges are ranges of devices on bus 0
 250                  * [ 3: 3] Reserved
 251                  * [ 6: 4] Destination Node
 252                  *         000 = Node 0
 253                  *         001 = Node 1
 254                  *         010 = Node 2
 255                  *         011 = Node 3
 256                  *         100 = Node 4
 257                  *         101 = Node 5
 258                  *         110 = Node 6
 259                  *         111 = Node 7
 260                  * [ 7: 7] Reserved
 261                  * [ 9: 8] Destination Link
 262                  *         00 = Link 0
 263                  *         01 = Link 1
 264                  *         10 = Link 2
 265                  *         11 - Reserved
 266                  * [15:10] Reserved
 267                  * [23:16] Bus Number Base i
 268                  *         This field defines the lowest bus number in configuration region i
 269                  * [31:24] Bus Number Limit i
 270                  *         This field defines the highest bus number in configuration region i
 271                  */
 272                 PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
 273                 PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 274                 PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 275                 PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 276
 277         };
 278
 279         int max;
 280         max = ARRAY_SIZE(register_values);
 281         setup_resource_map(register_values, max);
 282 }
 283