src/mainboard/supermicro/h8dme/get_bus_conf.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #include <console/console.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25 #include <string.h>
  26 #include <stdint.h>
  27 #if CONFIG_LOGICAL_CPUS==1
  28 #include <cpu/amd/dualcore.h>
  29 #endif
  30
  31 #include <cpu/amd/amdk8_sysconf.h>
  32 #include <stdlib.h>
  33
  34
  35 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
  36 //busnum is default
  37         unsigned char bus_isa;
  38         unsigned char bus_mcp55[8]; //1
  39         unsigned apicid_mcp55;
  40
  41         unsigned char bus_pcix[3]; // under bus_mcp55_2
  42
  43 unsigned pci1234x[] =
  44 {        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
  45          //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
  46         0x0000ff0,
  47         0x0000ff0,
  48 //        0x0000ff0,
  49 //        0x0000ff0,
  50 //        0x0000ff0,
  51 //        0x0000ff0,
  52 //        0x0000ff0,
  53 //        0x0000ff0
  54 };
  55 unsigned hcdnx[] =
  56 { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
  57         0x20202020,
  58         0x20202020,
  59 //        0x20202020,
  60 //        0x20202020,
  61 //        0x20202020,
  62 //        0x20202020,
  63 //        0x20202020,
  64 //        0x20202020,
  65 };
  66 unsigned sbdnb;
  67
  68 extern void get_sblk_pci1234(void);
  69
  70 static unsigned get_bus_conf_done = 0;
  71
  72 void get_bus_conf(void)
  73 {
  74
  75         unsigned apicid_base;
  76         unsigned sbdn;
  77
  78         device_t dev;
  79         int i;
  80
  81         if(get_bus_conf_done==1) return; //do it only once
  82
  83         get_bus_conf_done = 1;
  84
  85         sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
  86         for(i=0;i<sysconf.hc_possible_num; i++) {
  87                 sysconf.pci1234[i] = pci1234x[i];
  88                 sysconf.hcdn[i] = hcdnx[i];
  89         }
  90
  91         get_sblk_pci1234();
  92
  93         sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
  94         sbdn = sysconf.sbdn;
  95
  96         sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain
  97
  98         for(i=0; i<8; i++) {
  99                 bus_mcp55[i] = 0;
 100         }
 101
 102         for(i=0; i<3; i++) {
 103                 bus_pcix[i] = 0;
 104         }
 105
 106
 107         bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
 108
 109                 /* MCP55 */
 110                 dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06,0));
 111                 if (dev) {
 112                         bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 113                         bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 114                         bus_mcp55[2]++;
 115                 }
 116                 else {
 117                         printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06);
 118
 119                         bus_mcp55[1] = 2;
 120                         bus_mcp55[2] = 3;
 121                 }
 122
 123                 for(i=2; i<8;i++) {
 124                         dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0));
 125                         if (dev) {
 126                                 bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 127                                 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 128                                 bus_isa++;
 129                         }
 130                         else {
 131                                 printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 );
 132                                 bus_isa = bus_mcp55[i-1]+1;
 133                         }
 134                 }
 135
 136                 if(bus_mcp55[2]) {
 137                         for(i=0;i<2; i++) {
 138                                 dev = dev_find_slot(bus_mcp55[2], PCI_DEVFN(0, i));
 139                                 if(dev) {
 140                                         bus_pcix[0] = bus_mcp55[2];
 141                                         bus_pcix[i+1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 142                                 }
 143                         }
 144                 }
 145
 146
 147 /*I/O APICs:    APIC ID Version State           Address*/
 148 #if CONFIG_LOGICAL_CPUS==1
 149         apicid_base = get_apicid_base(1);
 150 #else
 151         apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
 152 #endif
 153         apicid_mcp55 = apicid_base+0;
 154
 155 }