src/mainboard/supermicro/h8dme/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## This program is free software; you can redistribute it and/or modify
   5 ## it under the terms of the GNU General Public License as published by
   6 ## the Free Software Foundation; either version 2 of the License, or
   7 ## (at your option) any later version.
   8 ##
   9 ## This program is distributed in the hope that it will be useful,
  10 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 ## GNU General Public License for more details.
  13 ##
  14 ## You should have received a copy of the GNU General Public License
  15 ## along with this program; if not, write to the Free Software
  16 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  17 ##
  18
  19 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
  20 default CONFIG_XIP_ROM_SIZE = 64 * 1024
  21 include /config/failovercalculation.lb
  22
  23 arch i386 end
  24
  25 ##
  26 ## Build the objects we have code for in this directory.
  27 ##
  28
  29 driver mainboard.o
  30 #needed by irq_tables and mptable and acpi_tables
  31 object get_bus_conf.o
  32
  33 if CONFIG_GENERATE_MP_TABLE object mptable.o end
  34 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
  35
  36         if CONFIG_USE_INIT
  37                 makerule ./auto.o
  38                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  39                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  40                 end
  41         else
  42                 makerule ./auto.inc
  43                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  44                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  45                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  46                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  47                 end
  48         end
  49
  50 if CONFIG_USE_FAILOVER_IMAGE
  51 else
  52     if CONFIG_AP_CODE_IN_CAR
  53         makerule ./apc_auto.o
  54                 depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
  55                 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
  56         end
  57         ldscript /arch/i386/init/ldscript_apc.lb
  58     end
  59 end
  60
  61
  62 ##
  63 ## Build our 16 bit and 32 bit coreboot entry code
  64 ##
  65 if CONFIG_HAVE_FAILOVER_BOOT
  66     if CONFIG_USE_FAILOVER_IMAGE
  67         mainboardinit cpu/x86/16bit/entry16.inc
  68         ldscript /cpu/x86/16bit/entry16.lds
  69     end
  70 else
  71     if CONFIG_USE_FALLBACK_IMAGE
  72         mainboardinit cpu/x86/16bit/entry16.inc
  73         ldscript /cpu/x86/16bit/entry16.lds
  74     end
  75 end
  76
  77 mainboardinit cpu/x86/32bit/entry32.inc
  78
  79         if CONFIG_USE_INIT
  80                 ldscript /cpu/x86/32bit/entry32.lds
  81         end
  82
  83         if CONFIG_USE_INIT
  84                 ldscript /cpu/amd/car/cache_as_ram.lds
  85         end
  86
  87 ##
  88 ## Build our reset vector (This is where coreboot is entered)
  89 ##
  90 if CONFIG_HAVE_FAILOVER_BOOT
  91     if CONFIG_USE_FAILOVER_IMAGE
  92         mainboardinit cpu/x86/16bit/reset16.inc
  93         ldscript /cpu/x86/16bit/reset16.lds
  94     else
  95         mainboardinit cpu/x86/32bit/reset32.inc
  96         ldscript /cpu/x86/32bit/reset32.lds
  97     end
  98 else
  99     if CONFIG_USE_FALLBACK_IMAGE
 100         mainboardinit cpu/x86/16bit/reset16.inc
 101         ldscript /cpu/x86/16bit/reset16.lds
 102     else
 103         mainboardinit cpu/x86/32bit/reset32.inc
 104         ldscript /cpu/x86/32bit/reset32.lds
 105     end
 106 end
 107
 108 ##
 109 ## Include an id string (For safe flashing)
 110 ##
 111 mainboardinit arch/i386/lib/id.inc
 112 ldscript /arch/i386/lib/id.lds
 113
 114 ##
 115 ## ROMSTRAP table for MCP55
 116 ##
 117 if CONFIG_HAVE_FAILOVER_BOOT
 118     if CONFIG_USE_FAILOVER_IMAGE
 119         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 120         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 121     end
 122 else
 123     if CONFIG_USE_FALLBACK_IMAGE
 124         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 125         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 126     end
 127 end
 128
 129         ##
 130         ## Setup Cache-As-Ram
 131         ##
 132         mainboardinit cpu/amd/car/cache_as_ram.inc
 133
 134 ###
 135 ### This is the early phase of coreboot startup
 136 ### Things are delicate and we test to see if we should
 137 ### failover to another image.
 138 ###
 139 if CONFIG_HAVE_FAILOVER_BOOT
 140     if CONFIG_USE_FAILOVER_IMAGE
 141                 ldscript /arch/i386/lib/failover_failover.lds
 142     end
 143 else
 144     if CONFIG_USE_FALLBACK_IMAGE
 145                 ldscript /arch/i386/lib/failover.lds
 146     end
 147 end
 148
 149 ##
 150 ## Setup RAM
 151 ##
 152         if CONFIG_USE_INIT
 153                 initobject auto.o
 154         else
 155                 mainboardinit ./auto.inc
 156         end
 157
 158 ##
 159 ## Include the secondary Configuration files
 160 ##
 161 config chip.h
 162
 163 chip northbridge/amd/amdk8/root_complex
 164         device apic_cluster 0 on
 165                 chip cpu/amd/socket_F
 166                         device apic 0 on end
 167                 end
 168         end
 169         device pci_domain 0 on
 170                 chip northbridge/amd/amdk8 #mc0
 171                         device pci 18.0 on end
 172                         device pci 18.0 on end
 173                         device pci 18.0 on
 174                                 #  devices on link 0, link 0 == LDT 0
 175                                 chip southbridge/nvidia/mcp55
 176                                         device pci 0.0 on end   # HT
 177                                         device pci 1.0 on # LPC
 178                                                 chip superio/winbond/w83627hf
 179                                                         device pnp 2e.0 off #  Floppy
 180                                                                 io 0x60 = 0x3f0
 181                                                                 irq 0x70 = 6
 182                                                                 drq 0x74 = 2
 183                                                         end
 184                                                         device pnp 2e.1 off #  Parallel Port
 185                                                                 io 0x60 = 0x378
 186                                                                 irq 0x70 = 7
 187                                                         end
 188                                                         device pnp 2e.2 on #  Com1
 189                                                                 io 0x60 = 0x3f8
 190                                                                 irq 0x70 = 4
 191                                                         end
 192                                                         device pnp 2e.3 off #  Com2
 193                                                                 io 0x60 = 0x2f8
 194                                                                 irq 0x70 = 3
 195                                                         end
 196                                                         device pnp 2e.5 on #  Keyboard
 197                                                                 io 0x60 = 0x60
 198                                                                 io 0x62 = 0x64
 199                                                                 irq 0x70 = 1
 200                                                                 irq 0x72 = 12
 201                                                         end
 202                                                         device pnp 2e.6 off  # SFI
 203                                                                 io 0x62 = 0x100
 204                                                         end
 205                                                         device pnp 2e.7 off #  GPIO_GAME_MIDI
 206                                                                 io 0x60 = 0x220
 207                                                                 io 0x62 = 0x300
 208                                                                 irq 0x70 = 9
 209                                                         end
 210                                                         device pnp 2e.8 off end #  WDTO_PLED
 211                                                         device pnp 2e.9 off end #  GPIO_SUSLED
 212                                                         device pnp 2e.a off end #  ACPI
 213                                                         device pnp 2e.b on #  HW Monitor
 214                                                                 io 0x60 = 0x290
 215                                                                 irq 0x70 = 5
 216                                                         end
 217                                                 end
 218                                         end
 219                                         device pci 1.1 on # SM 0
 220                                                 chip drivers/i2c/i2cmux2
 221                                                         device i2c 48 off end
 222                                                         device i2c 49 off end
 223                                                 end
 224                                         end # SM
 225                                         device pci 1.1 on # SM 1
 226 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 227 #                                                chip drivers/generic/generic #PCIXA Slot1
 228 #                                                        device i2c 50 on end
 229 #                                                end
 230 #                                                chip drivers/generic/generic #PCIXB Slot1
 231 #                                                        device i2c 51 on end
 232 #                                                end
 233 #                                                chip drivers/generic/generic #PCIXB Slot2
 234 #                                                        device i2c 52 on end
 235 #                                                end
 236 #                                                chip drivers/generic/generic #PCI Slot1
 237 #                                                        device i2c 53 on end
 238 #                                                end
 239 #                                                chip drivers/generic/generic #Master MCP55 PCI-E
 240 #                                                        device i2c 54 on end
 241 #                                                end
 242 #                                                chip drivers/generic/generic #Slave MCP55 PCI-E
 243 #                                                        device i2c 55 on end
 244 #                                                end
 245                                                 chip drivers/generic/generic #MAC EEPROM
 246                                                         device i2c 51 on end
 247                                                 end
 248
 249                                         end # SM
 250                                         device pci 2.0 on end # USB 1.1
 251                                         device pci 2.1 on end # USB 2
 252                                         device pci 4.0 on end # IDE
 253                                         device pci 5.0 on end # SATA 0
 254                                         device pci 5.1 on end # SATA 1
 255                                         device pci 5.2 on end # SATA 2
 256                                         device pci 6.0 on  # PCI
 257                                                 device pci 6.0 on end
 258                                         end
 259                                         device pci 6.1 on end # AZA
 260                                         device pci 8.0 on end # NIC
 261                                         device pci 9.0 on end # NIC
 262                                         device pci a.0 on  # PCI E 5
 263                                                 device pci 0.0 on #nec pci-x
 264                                                 end
 265                                                 device pci 0.1 on #nec pci-x
 266                                                         device pci 4.0 on end #scsi
 267                                                         device pci 4.1 on end #scsi
 268                                                 end
 269                                         end
 270                                         device pci b.0 on end # PCI E 4
 271                                         device pci c.0 on end # PCI E 3
 272                                         device pci d.0 on end # PCI E 2
 273                                         device pci e.0 on end # PCI E 1
 274                                         device pci f.0 on end # PCI E 0
 275                                         register "ide0_enable" = "1"
 276                                         register "sata0_enable" = "1"
 277                                         register "sata1_enable" = "1"
 278                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 279                                         register "mac_eeprom_addr" = "0x51"
 280                                 end
 281                         end #  device pci 18.0
 282                         device pci 18.1 on end
 283                         device pci 18.2 on end
 284                         device pci 18.3 on end
 285                 end # mc0
 286
 287         end # PCI domain
 288
 289 #       chip drivers/generic/debug
 290 #               device pnp 0.0 off end # chip name
 291 #                device pnp 0.1 on end # pci_regs_all
 292 #                device pnp 0.2 off end # mem
 293 #                device pnp 0.3 off end # cpuid
 294 #                device pnp 0.4 on end # smbus_regs_all
 295 #                device pnp 0.5 off end # dual core msr
 296 #                device pnp 0.6 off end # cache size
 297 #                device pnp 0.7 off end # tsc
 298 #                device pnp 0.8 off  end # io
 299 #                device pnp 0.9 on end # io
 300 #       end
 301 end #root_complex