src/mainboard/sunw/ultra40/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11
  12 #include <cpu/amd/model_fxx_rev.h>
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18
  19 #include "cpu/x86/lapic/boot_cpu.c"
  20 #include "northbridge/amd/amdk8/reset_test.c"
  21 #include "northbridge/amd/amdk8/debug.c"
  22 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  23
  24 #include "cpu/x86/mtrr/earlymtrr.c"
  25 #include "cpu/x86/bist.h"
  26
  27 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  28
  29 #include "northbridge/amd/amdk8/setup_resource_map.c"
  30
  31 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  32
  33 static void memreset(int controllers, const struct mem_controller *ctrl)
  34 {
  35 }
  36
  37 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  38
  39 #define SUPERIO_GPIO_IO_BASE 0x400
  40
  41 #ifdef ENABLE_ONBOARD_SCSI
  42 static void sio_gpio_setup(void)
  43 {
  44         unsigned value;
  45
  46         /*Enable onboard scsi*/
  47         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  48         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  49         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  50 }
  51 #endif
  52
  53 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  54 {
  55         /* nothing to do */
  56 }
  57
  58 static inline int spd_read_byte(unsigned device, unsigned address)
  59 {
  60         return smbus_read_byte(device, address);
  61 }
  62
  63 #include "northbridge/amd/amdk8/raminit.c"
  64 #include "northbridge/amd/amdk8/coherent_ht.c"
  65 #include "lib/generic_sdram.c"
  66
  67  /* tyan does not want the default */
  68 #include "resourcemap.c"
  69
  70 #include "cpu/amd/dualcore/dualcore.c"
  71
  72 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  73
  74 //set GPIO to input mode
  75 #define CK804_MB_SETUP \
  76                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
  77                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
  78                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
  79                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
  80                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
  81                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
  82
  83 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  84
  85
  86
  87 #include "cpu/amd/car/post_cache_as_ram.c"
  88
  89 #include "cpu/amd/model_fxx/init_cpus.c"
  90
  91 #include "northbridge/amd/amdk8/early_ht.c"
  92
  93 static void sio_setup(void)
  94 {
  95         unsigned value;
  96         uint32_t dword;
  97         uint8_t byte;
  98
  99         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 100
 101         byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 102         byte |= 0x20;
 103         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 104
 105         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 106         dword |= (1<<29)|(1<<0);
 107         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 108
 109         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 110
 111         value =  lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 112         value &= 0xbf;
 113         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 114 }
 115
 116 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 117 {
 118         static const uint16_t spd_addr [] = {
 119                         // Node 0
 120                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 121                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 122                         // Node 1
 123                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 124                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 125         };
 126
 127         int needs_reset;
 128         unsigned bsp_apicid = 0;
 129
 130         struct mem_controller ctrl[8];
 131         unsigned nodes;
 132
 133         if (!cpu_init_detectedx && boot_cpu()) {
 134                 /* Nothing special needs to be done to find bus 0 */
 135                 /* Allow the HT devices to be found */
 136
 137                 enumerate_ht_chain();
 138
 139                 sio_setup();
 140         }
 141
 142         if (bist == 0) {
 143                 bsp_apicid = init_cpus(cpu_init_detectedx);
 144         }
 145
 146         lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 147         uart_init();
 148         console_init();
 149
 150         /* Halt if there was a built in self test failure */
 151         report_bist_failure(bist);
 152
 153         setup_ultra40_resource_map();
 154
 155         needs_reset = setup_coherent_ht_domain();
 156
 157         wait_all_core0_started();
 158 #if CONFIG_LOGICAL_CPUS==1
 159         // It is said that we should start core1 after all core0 launched
 160         start_other_cores();
 161         wait_all_other_cores_started(bsp_apicid);
 162 #endif
 163
 164         needs_reset |= ht_setup_chains_x();
 165
 166         needs_reset |= ck804_early_setup_x();
 167
 168         if (needs_reset) {
 169                 print_info("ht reset -\n");
 170                 soft_reset();
 171         }
 172
 173         allow_all_aps_stop(bsp_apicid);
 174
 175         nodes = get_nodes();
 176         //It's the time to set ctrl now;
 177         fill_mem_ctrl(nodes, ctrl, spd_addr);
 178
 179         enable_smbus();
 180
 181         sdram_initialize(nodes, ctrl);
 182
 183         post_cache_as_ram();
 184 }
 185