src/mainboard/sunw/ultra40/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11 #include <spd.h>
  12
  13 #include <cpu/amd/model_fxx_rev.h>
  14 #include "northbridge/amd/amdk8/incoherent_ht.c"
  15 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/amd/model_fxx/apic_timer.c"
  18 #include "lib/delay.c"
  19
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  24
  25 #include "cpu/x86/mtrr/earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  29
  30 #include "northbridge/amd/amdk8/setup_resource_map.c"
  31
  32 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  33
  34 static void memreset(int controllers, const struct mem_controller *ctrl)
  35 {
  36 }
  37
  38 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  39
  40 #define SUPERIO_GPIO_IO_BASE 0x400
  41
  42 #ifdef ENABLE_ONBOARD_SCSI
  43 static void sio_gpio_setup(void)
  44 {
  45         unsigned value;
  46
  47         /*Enable onboard scsi*/
  48         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  49         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  50         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  51 }
  52 #endif
  53
  54 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  55 {
  56         /* nothing to do */
  57 }
  58
  59 static inline int spd_read_byte(unsigned device, unsigned address)
  60 {
  61         return smbus_read_byte(device, address);
  62 }
  63
  64 #include "northbridge/amd/amdk8/raminit.c"
  65 #include "northbridge/amd/amdk8/coherent_ht.c"
  66 #include "lib/generic_sdram.c"
  67
  68  /* tyan does not want the default */
  69 #include "resourcemap.c"
  70
  71 #include "cpu/amd/dualcore/dualcore.c"
  72
  73 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  74
  75 //set GPIO to input mode
  76 #define CK804_MB_SETUP \
  77                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
  78                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
  79                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
  80                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
  81                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
  82                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
  83
  84 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  85
  86
  87
  88 #include "cpu/amd/car/post_cache_as_ram.c"
  89
  90 #include "cpu/amd/model_fxx/init_cpus.c"
  91
  92 #include "northbridge/amd/amdk8/early_ht.c"
  93
  94 static void sio_setup(void)
  95 {
  96         unsigned value;
  97         uint32_t dword;
  98         uint8_t byte;
  99
 100         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 101
 102         byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 103         byte |= 0x20;
 104         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 105
 106         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 107         dword |= (1<<29)|(1<<0);
 108         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 109
 110         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 111
 112         value =  lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 113         value &= 0xbf;
 114         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 115 }
 116
 117 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 118 {
 119         static const uint16_t spd_addr [] = {
 120                         // Node 0
 121                         DIMM0, DIMM2, 0, 0,
 122                         DIMM1, DIMM3, 0, 0,
 123                         // Node 1
 124                         DIMM4, DIMM6, 0, 0,
 125                         DIMM5, DIMM7, 0, 0,
 126         };
 127
 128         int needs_reset;
 129         unsigned bsp_apicid = 0;
 130
 131         struct mem_controller ctrl[8];
 132         unsigned nodes;
 133
 134         if (!cpu_init_detectedx && boot_cpu()) {
 135                 /* Nothing special needs to be done to find bus 0 */
 136                 /* Allow the HT devices to be found */
 137
 138                 enumerate_ht_chain();
 139
 140                 sio_setup();
 141         }
 142
 143         if (bist == 0) {
 144                 bsp_apicid = init_cpus(cpu_init_detectedx);
 145         }
 146
 147         lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 148         uart_init();
 149         console_init();
 150
 151         /* Halt if there was a built in self test failure */
 152         report_bist_failure(bist);
 153
 154         setup_ultra40_resource_map();
 155
 156         needs_reset = setup_coherent_ht_domain();
 157
 158         wait_all_core0_started();
 159 #if CONFIG_LOGICAL_CPUS==1
 160         // It is said that we should start core1 after all core0 launched
 161         start_other_cores();
 162         wait_all_other_cores_started(bsp_apicid);
 163 #endif
 164
 165         needs_reset |= ht_setup_chains_x();
 166
 167         needs_reset |= ck804_early_setup_x();
 168
 169         if (needs_reset) {
 170                 print_info("ht reset -\n");
 171                 soft_reset();
 172         }
 173
 174         allow_all_aps_stop(bsp_apicid);
 175
 176         nodes = get_nodes();
 177         //It's the time to set ctrl now;
 178         fill_mem_ctrl(nodes, ctrl, spd_addr);
 179
 180         enable_smbus();
 181
 182         sdram_initialize(nodes, ctrl);
 183
 184         post_cache_as_ram();
 185 }
 186