1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
6 #include <cpu/amd/amdk8_sysconf.h>
8 extern unsigned char bus_isa;
9 extern unsigned char bus_ck804_0; //1
10 extern unsigned char bus_ck804_1; //2
11 extern unsigned char bus_ck804_2; //3
12 extern unsigned char bus_ck804_3; //4
13 extern unsigned char bus_ck804_4; //5
14 extern unsigned char bus_ck804_5; //6
15 extern unsigned char bus_8131_0; //7
16 extern unsigned char bus_8131_1; //8
17 extern unsigned char bus_8131_2; //9
18 extern unsigned char bus_ck804b_0;//a
19 extern unsigned char bus_ck804b_1;//b
20 extern unsigned char bus_ck804b_2;//c
21 extern unsigned char bus_ck804b_3;//d
22 extern unsigned char bus_ck804b_4;//e
23 extern unsigned char bus_ck804b_5;//f
24 extern unsigned apicid_ck804;
25 extern unsigned apicid_8131_1;
26 extern unsigned apicid_8131_2;
27 extern unsigned apicid_ck804b;
29 extern unsigned pci1234[];
32 extern unsigned hcdn[];
33 extern unsigned sbdn3;
34 extern unsigned sbdnb;
36 static void *smp_write_config_table(void *v)
38 static const char sig[4] = "PCMP";
39 static const char oem[8] = "COREBOOT";
40 static const char productid[12] = "ultra40 ";
41 struct mp_config_table *mc;
43 unsigned char bus_num;
46 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
47 memset(mc, 0, sizeof(*mc));
49 memcpy(mc->mpc_signature, sig, sizeof(sig));
50 mc->mpc_length = sizeof(*mc); /* initially just the header */
52 mc->mpc_checksum = 0; /* not yet computed */
53 memcpy(mc->mpc_oem, oem, sizeof(oem));
54 memcpy(mc->mpc_productid, productid, sizeof(productid));
57 mc->mpc_entry_count = 0; /* No entries yet... */
58 mc->mpc_lapic = LAPIC_ADDR;
63 smp_write_processors(mc);
68 /* define bus and isa numbers */
69 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
70 smp_write_bus(mc, bus_num, "PCI ");
72 smp_write_bus(mc, bus_isa, "ISA ");
74 /*I/O APICs: APIC ID Version State Address*/
80 dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
82 res = find_resource(dev, PCI_BASE_ADDRESS_1);
84 smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
87 /* Initialize interrupt mapping*/
90 pci_write_config32(dev, 0x7c, dword);
93 pci_write_config32(dev, 0x80, dword);
96 pci_write_config32(dev, 0x84, dword);
100 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
102 res = find_resource(dev, PCI_BASE_ADDRESS_0);
104 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
107 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
109 res = find_resource(dev, PCI_BASE_ADDRESS_0);
111 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
115 if(pci1234[2] & 0xf) {
116 dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
118 res = find_resource(dev, PCI_BASE_ADDRESS_1);
120 smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base);
124 pci_write_config32(dev, 0x7c, dword);
127 pci_write_config32(dev, 0x80, dword);
130 pci_write_config32(dev, 0x84, dword);
137 mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
139 // Onboard ck804 smbus
140 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
143 // Onboard ck804 USB 1.1
144 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
146 // Onboard ck804 USB 2
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
149 // Onboard ck804 Audio
150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
152 // Onboard ck804 SATA 0
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
155 // Onboard ck804 SATA 1
156 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
159 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
163 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
167 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
171 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4);
174 if(pci1234[2] & 0xf) {
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
180 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
186 //Slot 4 PCI-X 100/66
188 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4);
193 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29
198 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30
203 //Slot 6 PCIX 133/100/66
205 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24
208 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
209 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
210 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
211 /* There is no extension information... */
213 /* Compute the checksums */
214 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
215 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
216 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
217 mc, smp_next_mpe_entry(mc));
218 return smp_next_mpe_entry(mc);
221 unsigned long write_smp_table(unsigned long addr)
224 v = smp_write_floating_table(addr);
225 return (unsigned long)smp_write_config_table(v);