1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/nofailovercalculation.lb
4 default CONFIG_ROM_PAYLOAD = 1
10 ## Build the objects we have code for in this directory.
14 #needed by irq_tables and mptable and acpi_tables
17 if CONFIG_HAVE_MP_TABLE object mptable.o end
18 if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
22 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
23 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
27 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
28 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
29 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
30 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
35 ## Build our 16 bit and 32 bit coreboot entry code
37 if CONFIG_USE_FALLBACK_IMAGE
38 mainboardinit cpu/x86/16bit/entry16.inc
39 ldscript /cpu/x86/16bit/entry16.lds
42 mainboardinit cpu/x86/32bit/entry32.inc
45 ldscript /cpu/x86/32bit/entry32.lds
49 ldscript /cpu/amd/car/cache_as_ram.lds
53 ## Build our reset vector (This is where coreboot is entered)
55 if CONFIG_USE_FALLBACK_IMAGE
56 mainboardinit cpu/x86/16bit/reset16.inc
57 ldscript /cpu/x86/16bit/reset16.lds
59 mainboardinit cpu/x86/32bit/reset32.inc
60 ldscript /cpu/x86/32bit/reset32.lds
64 ## Include an id string (For safe flashing)
66 mainboardinit southbridge/nvidia/ck804/id.inc
67 ldscript /southbridge/nvidia/ck804/id.lds
70 ## ROMSTRAP table for CK804
72 if CONFIG_USE_FALLBACK_IMAGE
73 mainboardinit southbridge/nvidia/ck804/romstrap.inc
74 ldscript /southbridge/nvidia/ck804/romstrap.lds
80 mainboardinit cpu/amd/car/cache_as_ram.inc
83 ### This is the early phase of coreboot startup
84 ### Things are delicate and we test to see if we should
85 ### failover to another image.
87 if CONFIG_USE_FALLBACK_IMAGE
88 ldscript /arch/i386/lib/failover.lds
97 mainboardinit ./auto.inc
101 ## Include the secondary Configuration files
105 # sample config for tyan/s2895
106 chip northbridge/amd/amdk8/root_complex
107 device apic_cluster 0 on
108 chip cpu/amd/socket_940
112 device pci_domain 0 on
113 chip northbridge/amd/amdk8 #mc0
114 device pci 18.0 on end # link 0
115 device pci 18.0 on # link1
116 # devices on link 0, link 0 == LDT 0
117 chip southbridge/nvidia/ck804
118 device pci 0.0 on end # HT
119 device pci 1.0 on # LPC
120 chip superio/smsc/lpc47m10x
121 device pnp 2e.0 off # Floppy
126 device pnp 2e.3 off # Parallel Port
130 device pnp 2e.4 on # Com1
134 device pnp 2e.5 off # Com2
138 device pnp 2e.7 off # Keyboard
146 device pci 1.1 on # SM 0
147 chip drivers/generic/generic #dimm 0-0-0
150 chip drivers/generic/generic #dimm 0-0-1
153 chip drivers/generic/generic #dimm 0-1-0
156 chip drivers/generic/generic #dimm 0-1-1
159 chip drivers/generic/generic #dimm 1-0-0
162 chip drivers/generic/generic #dimm 1-0-1
165 chip drivers/generic/generic #dimm 1-1-0
168 chip drivers/generic/generic #dimm 1-1-1
172 device pci 1.1 on # SM 1
173 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
174 # chip drivers/generic/generic #PCIXA Slot1
175 # device i2c 50 on end
177 # chip drivers/generic/generic #PCIXB Slot1
178 # device i2c 51 on end
180 # chip drivers/generic/generic #PCIXB Slot2
181 # device i2c 52 on end
183 # chip drivers/generic/generic #PCI Slot1
184 # device i2c 53 on end
186 # chip drivers/generic/generic #Master CK804 PCI-E
187 # device i2c 54 on end
189 # chip drivers/generic/generic #Slave CK804 PCI-E
190 # device i2c 55 on end
192 chip drivers/generic/generic #MAC EEPROM
197 device pci 2.0 on end # USB 1.1
198 device pci 2.1 on end # USB 2
199 device pci 4.0 on end # ACI
200 device pci 4.1 off end # MCI
201 device pci 6.0 on end # IDE
202 device pci 7.0 on end # SATA 1
203 device pci 8.0 on end # SATA 0
204 device pci 9.0 on end # PCI
205 device pci a.0 on end # NIC
206 device pci b.0 off end # PCI E 3
207 device pci c.0 off end # PCI E 2
208 device pci d.0 off end # PCI E 1
209 device pci e.0 on end # PCI E 0
210 register "ide0_enable" = "1"
211 register "ide1_enable" = "1"
212 register "sata0_enable" = "1"
213 register "sata1_enable" = "1"
214 # register "nic_rom_address" = "0xfff80000" # 64k
215 # register "raid_rom_address" = "0xfff90000"
216 register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
217 register "mac_eeprom_addr" = "0x51"
219 end # device pci 18.0
220 device pci 18.0 on end # link 2
221 device pci 18.1 on end
222 device pci 18.2 on end
223 device pci 18.3 on end
226 chip northbridge/amd/amdk8
227 device pci 19.0 on end # link 0
229 # devices on link 1, link 1 == LDT 1
230 chip southbridge/nvidia/ck804
231 device pci 0.0 on end # HT
232 device pci 1.0 on end # LPC
233 device pci 1.1 off end # SM
234 device pci 2.0 off end # USB 1.1
235 device pci 2.1 off end # USB 2
236 device pci 4.0 off end # ACI
237 device pci 4.1 off end # MCI
238 device pci 6.0 off end # IDE
239 device pci 7.0 off end # SATA 1
240 device pci 8.0 off end # SATA 0
241 device pci 9.0 off end # PCI
242 device pci a.0 on end # NIC
243 device pci b.0 off end # PCI E 3
244 device pci c.0 off end # PCI E 2
245 device pci d.0 off end # PCI E 1
246 device pci e.0 on end # PCI E 0
247 # register "nic_rom_address" = "0xfff80000" # 64k
248 register "mac_eeprom_smbus" = "3"
249 register "mac_eeprom_addr" = "0x51"
251 end # device pci 19.0
253 device pci 19.0 on end
254 device pci 19.1 on end
255 device pci 19.2 on end
256 device pci 19.3 on end