2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
5 * Copyright (C) 2010 Siemens AG, Inc.
6 * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <arch/ioapic.h>
22 #include <cpu/x86/lapic_def.h>
24 DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
26 /* Data to be patched by the BIOS during POST */
27 /* Memory related values */
28 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
29 Name(HPBA, 0xFED00000) /* Base address of HPET table */
31 /* USB overcurrent mapping pins. */
43 Name(DSEN, 1) // Display Output Switching Enable
46 /* PIC IRQ mapping registers, C00h-C01h */
47 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
48 Field(PRQM, ByteAcc, NoLock, Preserve) {
50 PRQD, 0x00000008, /* Offset: 1h */
52 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
53 PINA, 0x00000008, /* Index 0 */
54 PINB, 0x00000008, /* Index 1 */
55 PINC, 0x00000008, /* Index 2 */
56 PIND, 0x00000008, /* Index 3 */
57 SINT, 0x00000008, /* Index 4 */
59 PINE, 0x00000008, /* Index 9 */
60 PINF, 0x00000008, /* Index A */
61 PING, 0x00000008, /* Index B */
62 PINH, 0x00000008, /* Index C */
65 /* PCI Error control register */
66 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
67 Field(PERC, ByteAcc, NoLock, Preserve) {
74 /* Client Management index/data registers */
75 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
76 Field(CMT, ByteAcc, NoLock, Preserve) {
78 /* Client Management Data register */
86 /* GPM Port register */
87 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
88 Field(GPT, ByteAcc, NoLock, Preserve) {
99 /* Flash ROM program enable register */
100 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
101 Field(FRE, ByteAcc, NoLock, Preserve) {
106 /* PM2 index/data registers */
107 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
108 Field(PM2R, ByteAcc, NoLock, Preserve) {
113 /* Power Management I/O registers */
114 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
115 Field(PIOR, ByteAcc, NoLock, Preserve) {
119 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
120 Offset(0x00), /* MiscControl */
124 Offset(0x01), /* MiscStatus */
128 Offset(0x04), /* SmiWakeUpEventEnable3 */
131 Offset(0x07), /* SmiWakeUpEventStatus3 */
134 Offset(0x10), /* AcpiEnable */
137 Offset(0x1C), /* ProgramIoEnable */
144 Offset(0x1D), /* IOMonitorStatus */
151 Offset(0x20), /* AcpiPmEvtBlk */
153 Offset(0x36), /* GEvtLevelConfig */
157 Offset(0x37), /* GPMLevelConfig0 */
164 Offset(0x38), /* GPMLevelConfig1 */
171 Offset(0x3B), /* PMEStatus1 */
180 Offset(0x55), /* SoftPciRst */
188 /* Offset(0x61), */ /* Options_1 */
192 Offset(0x65), /* UsbPMControl */
195 Offset(0x68), /* MiscEnable68 */
199 Offset(0x92), /* GEVENTIN */
202 Offset(0x96), /* GPM98IN */
205 Offset(0x9A), /* EnhanceControl */
208 Offset(0xA8), /* PIO7654Enable */
213 Offset(0xA9), /* PIO7654Status */
221 * First word is PM1_Status, Second word is PM1_Enable
223 OperationRegion(P1EB, SystemIO, APEB, 0x04)
224 Field(P1EB, ByteAcc, NoLock, Preserve) {
248 OperationRegion (GVAR, SystemMemory, 0xBADEAFFE, 0x100)
249 Field (GVAR, ByteAcc, NoLock, Preserve)
258 Name (IOLM,0xe0000000)
260 #include "acpi/platform.asl"
264 /* PCIe Configuration Space for 16 busses */
265 OperationRegion(PCFG, SystemMemory, PCBA, 0x2000000) /* PCIe reserved space for 31 busses */
266 Field(PCFG, ByteAcc, NoLock, Preserve) {
267 Offset(0x00090024), /* Byte offset to SATA BAR5 register 24h - Bus 0, Device 18, Function 0 */
269 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
280 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
283 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
285 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
287 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
289 P92E, 1, /* Port92 decode enable */
292 OperationRegion(BAR5, SystemMemory, STB5, 0x1000)
293 Field(BAR5, AnyAcc, NoLock, Preserve)
296 Offset(0x120), /* Port 0 Task file status */
302 Offset(0x128), /* Port 0 Serial ATA status */
306 Offset(0x12C), /* Port 0 Serial ATA control */
308 Offset(0x130), /* Port 0 Serial ATA error */
313 offset(0x1A0), /* Port 1 Task file status */
319 Offset(0x1A8), /* Port 1 Serial ATA status */
323 Offset(0x1AC), /* Port 1 Serial ATA control */
325 Offset(0x1B0), /* Port 1 Serial ATA error */
330 Offset(0x220), /* Port 2 Task file status */
336 Offset(0x228), /* Port 2 Serial ATA status */
340 Offset(0x22C), /* Port 2 Serial ATA control */
342 Offset(0x230), /* Port 2 Serial ATA error */
347 Offset(0x2A0), /* Port 3 Task file status */
353 Offset(0x2A8), /* Port 3 Serial ATA status */
357 Offset(0x2AC), /* Port 3 Serial ATA control */
359 Offset(0x2B0), /* Port 3 Serial ATA error */
364 #include "acpi/event.asl"
365 #include "acpi/routing.asl"
366 #include "acpi/usb.asl"
371 /* Start \_SB scope */
373 #include "acpi/globutil.asl"
375 Device(PWRB) { /* Start Power button device */
376 Name(_HID, EISAID("PNP0C0C"))
378 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
379 Name(_STA, 0x0B) /* sata is invisible */
382 /* Note: Only need HID on Primary Bus */
389 Name(_HID, EISAID("PNP0A03"))
390 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
392 Method(_BBN, 0) { /* Bus number = 0 */
397 /* DBGO("\\_SB\\PCI0\\_STA\n") */
398 Return(0x0B) /* Status is visible */
403 Name (_HID, EisaId ("PNP0C02"))
404 Name (MEM1, ResourceTemplate ()
406 Memory32Fixed (ReadWrite,
407 0x00000000, // Address Base
408 0x00000000, // Address Length
410 Memory32Fixed (ReadWrite,
411 0x00000000, // Address Base
412 0x00000000, // Address Length
415 Method (_CRS, 0, NotSerialized)
417 CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._BAS, MB01)
418 CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._LEN, ML01)
419 CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._BAS, MB02)
420 CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._LEN, ML02)
423 Store (IO_APIC_ADDR, MB01)
424 Store (LOCAL_APIC_ADDR, MB02)
434 If(PCIF){ Return(APR0) } /* APIC mode */
435 Return (PR0) /* PIC Mode */
438 OperationRegion (BAR1, PCI_Config, 0x14, 0x04)
439 Field (BAR1, ByteAcc, NoLock, Preserve)
444 /* Describe the Northbridge devices */
446 Name(_ADR, 0x00000000)
449 /* The internal GFX bridge */
451 Name(_ADR, 0x00010000)
452 Name(_PRW, Package() {0x18, 4})
453 Method(_PRT,0) { Return (APR1) }
457 Name (_ADR, 0x00050000)
460 /* Windows 2000 and Windows XP call _DOS to enable/disable
461 * Display Output Switching during init and while a switch
464 Store (And(Arg0, 7), DSEN)
466 Method (_STA, 0, NotSerialized)
473 /* The external GFX bridge */
475 Name(_ADR, 0x00020000)
476 Name(_PRW, Package() {0x18, 4})
478 If(PCIF){ Return(APS2) } /* APIC mode */
479 Return (PS2) /* PIC Mode */
483 /* Dev3 is also an external GFX bridge */
486 Name(_ADR, 0x00040000)
487 Name(_PRW, Package() {0x18, 4})
489 If(PCIF){ Return(APS4) } /* APIC mode */
490 Return (PS4) /* PIC Mode */
495 Name(_ADR, 0x00050000)
496 Name(_PRW, Package() {0x18, 4})
498 If(PCIF){ Return(APS5) } /* APIC mode */
499 Return (PS5) /* PIC Mode */
504 Name(_ADR, 0x00060000)
505 Name(_PRW, Package() {0x18, 4})
507 If(PCIF){ Return(APS6) } /* APIC mode */
508 Return (PS6) /* PIC Mode */
512 /* The onboard EtherNet chip */
514 Name(_ADR, 0x00070000)
515 Name(_PRW, Package() {0x18, 4})
517 If(PCIF){ Return(APS7) } /* APIC mode */
518 Return (PS7) /* PIC Mode */
524 Name(_ADR, 0x00140004)
525 Name(_PRW, Package() {4, 5}) // Phoenix doeas it so
527 If(PCIF){ Return(AP2P) } /* APIC Mode */
528 Return (PCIB) /* PIC Mode */
532 /* Describe the Southbridge devices */
534 Name(_ADR, 0x00120000)
535 #include "acpi/sata.asl"
539 Name(_ADR, 0x00130000)
540 Name(_PRW, Package() {0x0B, 3})
544 Name(_ADR, 0x00130001)
545 Name(_PRW, Package() {0x0B, 3})
549 Name(_ADR, 0x00130002)
550 Name(_PRW, Package() {0x0B, 3})
554 Name(_ADR, 0x00130003)
555 Name(_PRW, Package() {0x0B, 3})
559 Name(_ADR, 0x00130004)
560 Name(_PRW, Package() {0x0B, 3})
564 Name(_ADR, 0x00130005)
565 Name(_PRW, Package() {0x0B, 3})
569 Name(_ADR, 0x00140000)
572 /* Primary (and only) IDE channel */
574 Name(_ADR, 0x00140001)
575 #include "acpi/ide.asl"
579 Name(_ADR, 0x00140002)
580 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
581 Field(AZPD, AnyAcc, NoLock, Preserve) {
605 If(LEqual(LINX,1)){ /* If we are running Linux */
615 Name (_ADR, 0x00140003)
618 /* PIC IRQ mapping registers, C00h-C01h */
619 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
620 Field(PRQM, ByteAcc, NoLock, Preserve) {
622 PRQD, 0x00000008, /* Offset: 1h */
625 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
626 PINA, 0x00000008, /* Index 0 */
627 PINB, 0x00000008, /* Index 1 */
628 PINC, 0x00000008, /* Index 2 */
629 PIND, 0x00000008, /* Index 3 */
630 SINT, 0x00000008, /* Index 4 */
632 PINE, 0x00000008, /* Index 9 */
633 PINF, 0x00000008, /* Index A */
634 PING, 0x00000008, /* Index B */
635 PINH, 0x00000008, /* Index C */
638 Method(CIRQ, 0x00, NotSerialized)
651 Name(IRQB, ResourceTemplate(){
652 IRQ(Level,ActiveLow,Shared){10,11}
655 Name(IRQP, ResourceTemplate(){
656 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7}
659 Name(PITF, ResourceTemplate(){
660 IRQ(Level,ActiveLow,Exclusive){9}
664 Name(_HID, EISAID("PNP0C0F"))
669 Return(0x0B) /* sata is invisible */
671 Return(0x09) /* sata is disabled */
673 } /* End Method(_SB.INTA._STA) */
677 } /* End Method(_SB.INTA._DIS) */
680 Return(IRQB) // Return(IRQP)
681 } /* Method(_SB.INTA._PRS) */
684 Store (IRQB, Local0) //
685 CreateWordField(Local0, 0x1, IRQ0)
686 ShiftLeft(1, PINA, IRQ0)
688 } /* Method(_SB.INTA._CRS) */
690 CreateWordField(ARG0, 1, IRQ0)
691 /* Use lowest available IRQ */
692 FindSetRightBit(IRQ0, Local0)
695 } /* End Method(_SB.INTA._SRS) */
696 } /* End Device(INTA) */
699 Name(_HID, EISAID("PNP0C0F"))
704 Return(0x0B) /* sata is invisible */
706 Return(0x09) /* sata is disabled */
708 } /* End Method(_SB.INTB._STA) */
712 } /* End Method(_SB.INTB._DIS) */
715 Return(IRQB) // Return(IRQP)
716 } /* Method(_SB.INTB._PRS) */
719 Store (IRQB, Local0) // {10,11}
720 CreateWordField(Local0, 0x1, IRQ0)
721 ShiftLeft(1, PINB, IRQ0)
723 } /* Method(_SB.INTB._CRS) */
726 CreateWordField(ARG0, 1, IRQ0)
727 /* Use lowest available IRQ */
728 FindSetRightBit(IRQ0, Local0)
731 } /* End Method(_SB.INTB._SRS) */
732 } /* End Device(INTB) */
735 Name(_HID, EISAID("PNP0C0F"))
740 Return(0x0B) /* sata is invisible */
742 Return(0x09) /* sata is disabled */
744 } /* End Method(_SB.INTC._STA) */
748 } /* End Method(_SB.INTC._DIS) */
751 Return(IRQB) // Return(IRQP)
752 } /* Method(_SB.INTC._PRS) */
755 Store (IRQB, Local0) // {10,11}
756 CreateWordField(Local0, 0x1, IRQ0)
757 ShiftLeft(1, PINC, IRQ0)
759 } /* Method(_SB.INTC._CRS) */
762 CreateWordField(ARG0, 1, IRQ0)
763 /* Use lowest available IRQ */
764 FindSetRightBit(IRQ0, Local0)
767 } /* End Method(_SB.INTC._SRS) */
768 } /* End Device(INTC) */
771 Name(_HID, EISAID("PNP0C0F"))
776 Return(0x0B) /* sata is invisible */
778 Return(0x09) /* sata is disabled */
780 } /* End Method(_SB.INTD._STA) */
784 } /* End Method(_SB.INTD._DIS) */
787 Return(IRQB) // Return(IRQP)
788 } /* Method(_SB.INTD._PRS) */
791 Store (IRQB, Local0) // {10,11}
792 CreateWordField(Local0, 0x1, IRQ0)
793 ShiftLeft(1, PIND, IRQ0)
795 } /* Method(_SB.INTD._CRS) */
798 CreateWordField(ARG0, 1, IRQ0)
799 /* Use lowest available IRQ */
800 FindSetRightBit(IRQ0, Local0)
803 } /* End Method(_SB.INTD._SRS) */
804 } /* End Device(INTD) */
807 Name(_HID, EISAID("PNP0C0F"))
812 Return(0x0B) /* sata is invisible */
814 Return(0x09) /* sata is disabled */
816 } /* End Method(_SB.INTE._STA) */
820 } /* End Method(_SB.INTE._DIS) */
823 Return(IRQB) // Return(IRQP)
827 Store (IRQB, Local0) // {10,11}
828 CreateWordField(Local0, 0x1, IRQ0)
829 ShiftLeft(1, PINE, IRQ0)
831 } /* Method(_SB.INTE._CRS) */
834 CreateWordField(ARG0, 1, IRQ0)
835 /* Use lowest available IRQ */
836 FindSetRightBit(IRQ0, Local0)
839 } /* End Method(_SB.INTE._SRS) */
840 } /* End Device(INTE) */
843 Name(_HID, EISAID("PNP0C0F"))
848 Return(0x0B) /* sata is invisible */
850 Return(0x09) /* sata is disabled */
852 } /* End Method(_SB.INTF._STA) */
856 } /* End Method(_SB.INTF._DIS) */
859 Return(IRQB) // Return(PITF)
860 } /* Method(_SB.INTF._PRS) */
863 Store (IRQB, Local0) // {10,11}
864 CreateWordField(Local0, 0x1, IRQ0)
865 ShiftLeft(1, PINF, IRQ0)
867 } /* Method(_SB.INTF._CRS) */
870 CreateWordField(ARG0, 1, IRQ0)
871 /* Use lowest available IRQ */
872 FindSetRightBit(IRQ0, Local0)
875 } /* End Method(_SB.INTF._SRS) */
876 } /* End Device(INTF) */
879 Name(_HID, EISAID("PNP0C0F"))
884 Return(0x0B) /* sata is invisible */
886 Return(0x09) /* sata is disabled */
888 } /* End Method(_SB.INTG._STA) */
892 } /* End Method(_SB.INTG._DIS) */
895 Return(IRQB) // Return(IRQP)
896 } /* Method(_SB.INTG._CRS) */
899 Store (IRQB, Local0) // {10,11}
900 CreateWordField(Local0, 0x1, IRQ0)
901 ShiftLeft(1, PING, IRQ0)
903 } /* Method(_SB.INTG._CRS) */
906 CreateWordField(ARG0, 1, IRQ0)
907 /* Use lowest available IRQ */
908 FindSetRightBit(IRQ0, Local0)
911 } /* End Method(_SB.INTG._SRS) */
912 } /* End Device(INTG) */
915 Name(_HID, EISAID("PNP0C0F"))
920 Return(0x0B) /* sata is invisible */
922 Return(0x09) /* sata is disabled */
924 } /* End Method(_SB.INTH._STA) */
928 } /* End Method(_SB.INTH._DIS) */
931 Return(IRQB) // Return(IRQP)
932 } /* Method(_SB.INTH._CRS) */
935 Store (IRQB, Local0) // {10,11}
936 CreateWordField(Local0, 0x1, IRQ0)
937 ShiftLeft(1, PINH, IRQ0)
939 } /* Method(_SB.INTH._CRS) */
942 CreateWordField(ARG0, 1, IRQ0)
943 /* Use lowest available IRQ */
944 FindSetRightBit(IRQ0, Local0)
947 } /* End Method(_SB.INTH._SRS) */
948 } /* End Device(INTH) */
951 /* Real Time Clock Device */
953 Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible)*/
954 Name(_CRS, ResourceTemplate() {
955 IRQ (Edge, ActiveHigh, Exclusive, ) {8}
956 IO(Decode16,0x0070, 0x0070, 1, 2)
957 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
959 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
961 Device(TMR) { /* Timer */
962 Name(_HID,EISAID("PNP0100")) /* System Timer */
963 Name(_CRS, ResourceTemplate() {
964 IRQ (Edge, ActiveHigh, Exclusive, ) {0}
965 IO(Decode16, 0x0040, 0x0040, 1, 4)
966 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
968 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
970 Device(SPKR) { /* Speaker */
971 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
972 Name(_CRS, ResourceTemplate() {
973 IO(Decode16, 0x0061, 0x0061, 1, 1)
975 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
978 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
979 Name(_CRS, ResourceTemplate() {
980 IRQ (Edge, ActiveHigh, Exclusive, ) {2}
981 IO(Decode16,0x0020, 0x0020, 1, 2)
982 IO(Decode16,0x00A0, 0x00A0, 0, 2)
983 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
984 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
986 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
988 Device(MAD) { /* 8257 DMA */
989 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
990 Name(_CRS, ResourceTemplate() {
991 DMA(Compatibility,NotBusMaster,Transfer8_16){4}
992 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
993 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
994 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
995 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
996 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
997 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
998 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
999 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1002 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1003 Name(_CRS, ResourceTemplate() {
1004 IO(Decode16, 0x00F0, 0x00F0, 1, 0x10)
1005 IRQ (Edge, ActiveHigh, Exclusive, ) {13}
1007 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1010 Name(_HID,EISAID("PNP0103"))
1011 Name(CRS,ResourceTemplate() {
1012 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
1015 Return(0x0F) /* sata is visible */
1018 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1026 Name (_HID, EisaId ("PNP0303"))
1027 Name (_CRS, ResourceTemplate ()
1030 0x0060, // Range Minimum
1031 0x0060, // Range Maximum
1036 0x0064, // Range Minimum
1037 0x0064, // Range Maximum
1041 IRQ (Edge, ActiveHigh, Exclusive, ) {1}
1047 Name (_HID, EisaId ("PNP0F13"))
1048 Name (_CRS, ResourceTemplate ()
1050 IRQ (Edge, ActiveHigh, Exclusive, ) {12}
1056 Name(_ADR, 0x00140005)
1057 Name (_PRW, Package (0x02)
1062 } /* end Ac97audio */
1065 Name(_ADR, 0x00140006)
1066 Name (_PRW, Package (0x02)
1071 } /* end Ac97modem */
1073 /* ITE IT8712F Support */
1074 OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
1075 Field (IOID, ByteAcc, NoLock, Preserve)
1077 SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
1080 IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
1083 LDN, 8, /* Logical Device Number */
1085 CID1, 8, /* Chip ID Byte 1, 0x87 */
1086 CID2, 8, /* Chip ID Byte 2, 0x12 */
1088 ACTR, 8, /* Function activate */
1090 APC0, 8, /* APC/PME Event Enable Register */
1091 APC1, 8, /* APC/PME Status Register */
1092 APC2, 8, /* APC/PME Control Register 1 */
1093 APC3, 8, /* Environment Controller Special Configuration Register */
1094 APC4, 8 /* APC/PME Control Register 2 */
1097 /* Enter the IT8712F MB PnP Mode */
1103 Store(0x55, SIOI) /* IT8712F magic number */
1105 /* Exit the IT8712F MB PnP Mode */
1113 * Keyboard PME is routed to SB600 Gevent3. We can wake
1114 * up the system by pressing the key.
1118 /* We only enable KBD PME for S5. */
1119 If (LLess (Arg0, 0x05))
1122 /* DBGO("IT8712F\n") */
1125 Store (One, ACTR) /* Enable EC */
1129 */ /* falling edge. which mode? Not sure. */
1132 Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
1134 Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
1143 Store (Zero, APC0) /* disable keyboard PME */
1145 Store (0xFF, APC1) /* clear keyboard PME status */
1149 /* ############################################################################################### */
1150 Name(CRES, ResourceTemplate() {
1151 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1153 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1154 0x0000, /* address granularity */
1155 0x0000, /* range minimum */
1156 0x0CF7, /* range maximum */
1157 0x0000, /* translation */
1161 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1162 0x0000, /* address granularity */
1163 0x0D00, /* range minimum */
1164 0xFFFF, /* range maximum */
1165 0x0000, /* translation */
1169 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
1170 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
1171 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
1173 /* DRAM Memory from 1MB to TopMem */
1174 DWORDMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0, 0, 0, 0x00, 1, ,, EMM2)
1175 WORDIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x00, 0x0D00, 0xffff, 0x00, 0xf300)
1176 }) /* End Name(_SB.PCI0.CRES) */
1180 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1182 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1183 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1185 CreateDWordField(CRES, ^EMM2._MIN, EM2B)
1186 CreateDWordField(CRES, ^EMM2._MAX, EM2E)
1187 CreateDWordField(CRES, ^EMM2._LEN, EM2L)
1190 Subtract(IOLM, 1, EM2E)
1191 Subtract(IOLM, TOM1, EM2L)
1193 If(LGreater(LOMH, 0xC0000)){
1194 Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
1195 Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
1198 Return(CRES) /* note to change the Name buffer */
1200 /* ########################################################################################## */
1201 } /* End Device(PCI0) */
1202 } /* End \_SB scope */
1206 /* DBGO("\\_SI\\_SST\n") */
1207 /* DBGO(" New Indicator state: ") */
1211 } /* End Scope SI */
1214 OperationRegion (SMB0, SystemIO, 0xB00, 0x10) // 0x0C replace by 0x10
1215 Field (SMB0, ByteAcc, NoLock, Preserve) {
1216 HSTS, 8, /* SMBUS status */
1217 SSTS, 8, /* SMBUS slave status */
1218 HCNT, 8, /* SMBUS control */
1219 HCMD, 8, /* SMBUS host cmd */
1220 HADD, 8, /* SMBUS address */
1221 DAT0, 8, /* SMBUS data0 */
1222 DAT1, 8, /* SMBUS data1 */
1223 BLKD, 8, /* SMBUS block data */
1224 SCNT, 8, /* SMBUS slave control */
1225 SCMD, 8, /* SMBUS shaow cmd */
1226 SEVT, 8, /* SMBUS slave event */
1227 SDAT, 8, /* SMBUS slave data */
1234 Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
1236 Store (0xFA, Local0)
1237 While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
1245 Method (SWTC, 1, NotSerialized) {
1246 Store (Arg0, Local0)
1247 Store (0x07, Local2)
1249 While (LEqual (Local1, One)) {
1250 Store (And (HSTS, 0x1E), Local3)
1251 If (LNotEqual (Local3, Zero)) { /* read sucess */
1252 If (LEqual (Local3, 0x02)) {
1253 Store (Zero, Local2)
1256 Store (Zero, Local1)
1259 If (LLess (Local0, 0x0A)) { /* read failure */
1260 Store (0x10, Local2)
1261 Store (Zero, Local1)
1264 Sleep (0x0A) /* 10 ms, try again */
1265 Subtract (Local0, 0x0A, Local0)
1273 Method (SMBR, 3, NotSerialized) {
1274 Store (0x07, Local0)
1275 If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
1276 Store (WCLR (), Local0) /* clear SMBUS status register before read data */
1277 If (LEqual (Local0, Zero)) {
1283 Store (Or (ShiftLeft (Arg1, One), One), HADD)
1285 If (LEqual (Arg0, 0x07)) {
1286 Store (0x48, HCNT) /* read byte */
1289 Store (SWTC (0x03E8), Local1) /* 1000 ms */
1290 If (LEqual (Local1, Zero)) {
1291 If (LEqual (Arg0, 0x07)) {
1292 Store (DAT0, Local0)
1296 Store (Local1, Local0)
1302 /* DBGO("the value of SMBusData0 register ") */
1310 #include "acpi/thermal.asl"