2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
27 #include <arch/romcc_io.h>
28 #include <device/pci_def.h>
29 #include <device/pnp_def.h>
30 #include <cpu/x86/lapic.h>
32 #include <pc80/mc146818rtc.h>
33 #include <console/console.h>
35 #include <cpu/x86/bist.h>
36 #include "northbridge/intel/i945/i945.h"
37 #include "northbridge/intel/i945/raminit.h"
38 #include "southbridge/intel/i82801gx/i82801gx.h"
40 void enable_smbus(void);
42 void setup_ich7_gpios(void)
44 printk(BIOS_DEBUG, " GPIOS...");
45 /* General Registers */
46 outl(0xbfc0f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
47 outl(0x70a87d83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
48 outl(0x7dc07f83, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
49 /* Output Control Registers */
50 outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
51 /* Input Control Registers */
52 outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
53 outl(0x000100e8, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
54 outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
55 outl(0x00010030, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
58 static void ich7_enable_lpc(void)
61 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
63 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
65 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
67 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1);
68 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c);
70 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601);
72 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
75 /* This box has two superios, so enabling serial becomes slightly excessive.
76 * We disable a lot of stuff to make sure that there are no conflicts between
77 * the two. Also set up the GPIOs from the beginning. This is the "no schematic
78 * but safe anyways" method.
80 static inline void pnp_enter_ext_func_mode(device_t dev)
82 unsigned int port = dev >> 8;
86 static void pnp_exit_ext_func_mode(device_t dev)
88 unsigned int port = dev >> 8;
92 static void pnp_write_register(device_t dev, int reg, int val)
94 unsigned int port = dev >> 8;
99 static void early_superio_config(void)
103 dev=PNP_DEV(0x2e, 0x00);
105 pnp_enter_ext_func_mode(dev);
106 pnp_write_register(dev, 0x01, 0x94); // Extended Parport modes
107 pnp_write_register(dev, 0x02, 0x88); // UART power on
108 pnp_write_register(dev, 0x03, 0x72); // Floppy
109 pnp_write_register(dev, 0x04, 0x01); // EPP + SPP
110 pnp_write_register(dev, 0x14, 0x03); // Floppy
111 pnp_write_register(dev, 0x20, (0x3f0 >> 2)); // Floppy
112 pnp_write_register(dev, 0x23, (0x378 >> 2)); // PP base
113 pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
114 pnp_write_register(dev, 0x25, (0x2f8 >> 2)); // UART2 base
115 pnp_write_register(dev, 0x26, (2 << 4) | 0); // FDC + PP DMA
116 pnp_write_register(dev, 0x27, (6 << 4) | 7); // FDC + PP DMA
117 pnp_write_register(dev, 0x28, (4 << 4) | 3); // UART1,2 IRQ
118 /* These are the SMI status registers in the SIO: */
119 pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
121 pnp_write_register(dev, 0x31, 0x00); // GPIO1 DIR
122 pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL
123 pnp_write_register(dev, 0x33, 0x40); // GPIO2 DIR
124 pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL
125 pnp_write_register(dev, 0x35, 0xff); // GPIO3 DIR
126 pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL
127 pnp_write_register(dev, 0x37, 0xe0); // GPIO4 DIR
128 pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL
129 pnp_write_register(dev, 0x39, 0x80); // GPIO4 POL
131 pnp_exit_ext_func_mode(dev);
134 static void rcba_config(void)
136 /* Set up virtual channel 0 */
137 //RCBA32(0x0014) = 0x80000001;
138 //RCBA32(0x001c) = 0x03128010;
140 /* Device 1f interrupt pin register */
141 RCBA32(0x3100) = 0x00042220;
142 /* Device 1d interrupt pin register */
143 RCBA32(0x310c) = 0x00214321;
145 /* dev irq route register */
146 RCBA16(0x3140) = 0x0232;
147 RCBA16(0x3142) = 0x3246;
148 RCBA16(0x3144) = 0x0237;
149 RCBA16(0x3146) = 0x3201;
150 RCBA16(0x3148) = 0x3216;
153 RCBA8(0x31ff) = 0x03;
155 /* Enable upper 128bytes of CMOS */
156 RCBA32(0x3400) = (1 << 2);
158 /* Disable unused devices */
159 RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 |
160 FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA;
161 RCBA32(0x3418) |= (1 << 0); // Required.
163 /* Enable PCIe Root Port Clock Gate */
164 // RCBA32(0x341c) = 0x00000001;
166 /* This should probably go into the ACPI OS Init trap */
168 /* Set up I/O Trap #0 for 0xfe00 (SMIC) */
169 RCBA32(0x1e84) = 0x00020001;
170 RCBA32(0x1e80) = 0x0000fe01;
172 /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
173 RCBA32(0x1e9c) = 0x000200f0;
174 RCBA32(0x1e98) = 0x000c0801;
177 static void early_ich7_init(void)
182 // program secondary mlt XXX byte?
183 pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
185 // reset rtc power status
186 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
188 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
190 // usb transient disconnect
191 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
193 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
195 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
196 reg32 |= (1 << 29) | (1 << 17);
197 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
199 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
200 reg32 |= (1 << 31) | (1 << 27);
201 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
203 RCBA32(0x0088) = 0x0011d000;
204 RCBA16(0x01fc) = 0x060f;
205 RCBA32(0x01f4) = 0x86000040;
206 RCBA32(0x0214) = 0x10030549;
207 RCBA32(0x0218) = 0x00020504;
208 RCBA8(0x0220) = 0xc5;
209 reg32 = RCBA32(0x3410);
211 RCBA32(0x3410) = reg32;
212 reg32 = RCBA32(0x3430);
215 RCBA32(0x3430) = reg32;
216 RCBA32(0x3418) |= (1 << 0);
217 RCBA16(0x0200) = 0x2008;
218 RCBA8(0x2027) = 0x0d;
219 RCBA16(0x3e08) |= (1 << 7);
220 RCBA16(0x3e48) |= (1 << 7);
221 RCBA32(0x3e0e) |= (1 << 7);
222 RCBA32(0x3e4e) |= (1 << 7);
224 // next step only on ich7m b0 and later:
225 reg32 = RCBA32(0x2034);
226 reg32 &= ~(0x0f << 16);
228 RCBA32(0x2034) = reg32;
231 static void init_artec_dongle(void)
233 // Enable 4MB decoding
240 // Now, this needs to be included because it relies on the symbol
241 // __PRE_RAM__ being set during CAR stage (in order to compile the
242 // BSS free versions of the functions). Either rewrite the code
243 // to be always BSS free, or invent a flag that's better suited than
244 // __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
246 #include "lib/cbmem.c"
248 void main(unsigned long bist)
258 pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
260 pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
263 early_superio_config();
265 /* Set up the console */
269 i82801gx_enable_usbdebug(1);
270 early_usbdebug_init();
275 /* Halt if there was a built in self test failure */
276 report_bist_failure(bist);
278 if (MCHBAR16(SSKPD) == 0xCAFE) {
279 printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
281 while (1) asm("hlt");
284 /* Perform some early chipset initialization required
285 * before RAM initialization can work
287 i945_early_initialization();
289 /* This has to happen after i945_early_initialization() */
293 reg32 = inl(DEFAULT_PMBASE + 0x04);
294 printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
295 if (((reg32 >> 10) & 7) == 5) {
296 #if CONFIG_HAVE_ACPI_RESUME
297 printk(BIOS_DEBUG, "Resume from S3 detected.\n");
299 /* Clear SLP_TYPE. This will break stage2 but
300 * we care for that when we get there.
302 outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
305 printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
309 /* Enable SPD ROMs and DDR-II DRAM */
312 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
313 dump_spd_registers();
316 sdram_initialize(boot_mode);
318 /* Perform some initialization that must run before stage2 */
321 /* This should probably go away. Until now it is required
322 * and mainboard specific
326 /* Chipset Errata! */
329 /* Initialize the internal PCIe links before we go into stage2 */
330 i945_late_initialization();
332 #if !CONFIG_HAVE_ACPI_RESUME
333 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
334 #if CONFIG_DEBUG_RAM_SETUP
335 sdram_dump_mchbar_registers();
338 /* This will not work if TSEG is in place! */
339 u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
341 printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
342 ram_check(0x00000000, 0x000a0000);
343 ram_check(0x00100000, tom);
349 MCHBAR16(SSKPD) = 0xCAFE;
351 #if CONFIG_HAVE_ACPI_RESUME
352 /* Start address of high memory tables */
353 unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
355 /* If there is no high memory area, we didn't boot before, so
356 * this is not a resume. In that case we just create the cbmem toc.
358 if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
359 void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
361 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
362 * through stage 2. We could keep stuff like stack and heap in high tables
363 * memory completely, but that's a wonderful clean up task for another
366 if (resume_backup_memory)
367 memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
369 /* Magic for S3 resume */
370 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);