Since some people disapprove of white space cleanups mixed in regular commits
[coreboot.git] / src / mainboard / roda / rk886ex / cmos.layout
1 #
2 # This file is part of the coreboot project.
3 #
4 # Copyright (C) 2007-2008 coresystems GmbH
5 #
6 # This program is free software; you can redistribute it and/or
7 # modify it under the terms of the GNU General Public License as
8 # published by the Free Software Foundation; version 2 of
9 # the License.
10 #
11 # This program is distributed in the hope that it will be useful,
12 # but WITHOUT ANY WARRANTY; without even the implied warranty of
13 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 # GNU General Public License for more details.
15 #
16 # You should have received a copy of the GNU General Public License
17 # along with this program; if not, write to the Free Software
18 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
19 # MA 02110-1301 USA
20 #
21
22 # -----------------------------------------------------------------
23 entries
24
25 #start-bit length  config config-ID    name
26 #0            8       r       0        seconds
27 #8            8       r       0        alarm_seconds
28 #16           8       r       0        minutes
29 #24           8       r       0        alarm_minutes
30 #32           8       r       0        hours
31 #40           8       r       0        alarm_hours
32 #48           8       r       0        day_of_week
33 #56           8       r       0        day_of_month
34 #64           8       r       0        month
35 #72           8       r       0        year
36 # -----------------------------------------------------------------
37 # Status Register A
38 #80           4       r       0        rate_select
39 #84           3       r       0        REF_Clock
40 #87           1       r       0        UIP
41 # -----------------------------------------------------------------
42 # Status Register B
43 #88           1       r       0        auto_switch_DST
44 #89           1       r       0        24_hour_mode
45 #90           1       r       0        binary_values_enable
46 #91           1       r       0        square-wave_out_enable
47 #92           1       r       0        update_finished_enable
48 #93           1       r       0        alarm_interrupt_enable
49 #94           1       r       0        periodic_interrupt_enable
50 #95           1       r       0        disable_clock_updates
51 # -----------------------------------------------------------------
52 # Status Register C
53 #96           4       r       0        status_c_rsvd
54 #100          1       r       0        uf_flag
55 #101          1       r       0        af_flag
56 #102          1       r       0        pf_flag
57 #103          1       r       0        irqf_flag
58 # -----------------------------------------------------------------
59 # Status Register D
60 #104          7       r       0        status_d_rsvd
61 #111          1       r       0        valid_cmos_ram
62 # -----------------------------------------------------------------
63 # Diagnostic Status Register
64 #112          8       r       0        diag_rsvd1
65
66 # -----------------------------------------------------------------
67 0          120       r       0        reserved_memory
68 #120        264       r       0        unused
69
70 # -----------------------------------------------------------------
71 # RTC_BOOT_BYTE (coreboot hardcoded)
72 384          1       e       4        boot_option
73 385          1       e       4        last_boot
74 388          4       r       0        reboot_bits
75 #390          2       r       0        unused?
76
77 # -----------------------------------------------------------------
78 # coreboot config options: console
79 392          3       e       5        baud_rate
80 395          4       e       6        debug_level
81 #399          1       r       0        unused
82
83 # coreboot config options: cpu
84 400          1       e       2        hyper_threading
85 #401          7       r       0        unused
86
87 # coreboot config options: southbridge
88 408          1       e       1        nmi
89 #409          2       e       7        power_on_after_fail
90 #411          5       r       0        unused
91
92 # coreboot config options: bootloader
93 416        512       s       0        boot_devices
94 #928         80       r       0        unused
95
96 # coreboot config options: check sums
97 984         16       h       0        check_sum
98 #1000        24       r       0        amd_reserved
99
100 # ram initialization internal data
101 1024         8       r       0        C0WL0REOST
102 1032         8       r       0        C1WL0REOST
103 1040         8       r       0        RCVENMT
104 1048         4       r       0        C0DRT1
105 1052         4       r       0        C1DRT1
106
107 # -----------------------------------------------------------------
108
109 enumerations
110
111 #ID value   text
112 1     0     Disable
113 1     1     Enable
114 2     0     Enable
115 2     1     Disable
116 4     0     Fallback
117 4     1     Normal
118 5     0     115200
119 5     1     57600
120 5     2     38400
121 5     3     19200
122 5     4     9600
123 5     5     4800
124 5     6     2400
125 5     7     1200
126 6     1     Emergency
127 6     2     Alert
128 6     3     Critical
129 6     4     Error
130 6     5     Warning
131 6     6     Notice
132 6     7     Info
133 6     8     Debug
134 6     9     Spew
135 7     0     Disable
136 7     1     Enable
137 7     2     Keep
138
139 # -----------------------------------------------------------------
140 checksums
141
142 checksum 392 983 984
143
144